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gpu: nvgpu: gr: fix misra 2.7 violations

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Advisory Rule 2.7 states that there should be no unused
parameters in functions.

This patch removes the unused 'post_event', 'fault_ch' and
'hww_global_esr' parameters from the following:

 * gv11b_gr_intr_handle_l1_tag_exception()
 * gv11b_gr_intr_handle_lrf_exception()
 * gv11b_gr_intr_handle_cbu_exception()
 * gv11b_gr_intr_handle_l1_data_exception()
 * gv11b_gr_intr_handle_icache_exception()

These changes allowed the same parameters to be removed from the
the gr.intr.handle_tpc_sm_ecc_exception() interface.

Jira NVGPU-3178

Change-Id: I4d5dcbf2a5325e38782cdac67f9dd0b223fa1a18
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171220
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Scott Long
2019-08-08 10:19:12 -07:00
committed by mobile promotions
parent c61aab0cbc
commit bd021a1704
4 changed files with 14 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/common/gr/gr_intr.c
View File

@@ -80,8 +80,7 @@ static int gr_intr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc,
"GPC%d TPC%d: SM exception pending", gpc, tpc);
if (g->ops.gr.intr.handle_tpc_sm_ecc_exception != NULL) {
g->ops.gr.intr.handle_tpc_sm_ecc_exception(g, gpc, tpc,
post_event, fault_ch, hww_global_esr);
g->ops.gr.intr.handle_tpc_sm_ecc_exception(g, gpc, tpc);
}
g->ops.gr.intr.get_esr_sm_sel(g, gpc, tpc, &esr_sm_sel);

4
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
View File

@@ -92,9 +92,7 @@ void gv11b_gr_intr_enable_gpc_exceptions(struct gk20a *g,
void gv11b_gr_intr_set_hww_esr_report_mask(struct gk20a *g);
void gv11b_gr_intr_handle_tpc_sm_ecc_exception(struct gk20a *g,
u32 gpc, u32 tpc,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr);
u32 gpc, u32 tpc);
void gv11b_gr_intr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel);
void gv11b_gr_intr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,

34
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
View File

@@ -959,9 +959,7 @@ static void gv11b_gr_intr_report_l1_tag_corrected_err(struct gk20a *g,
}
}
static void gv11b_gr_intr_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr)
static void gv11b_gr_intr_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc)
{
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
@@ -1058,9 +1056,7 @@ static void gv11b_gr_intr_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32
gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f());
}
static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr)
static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc)
{
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
@@ -1176,9 +1172,7 @@ static void gv11b_gr_intr_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc
gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f());
}
static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr)
static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc)
{
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
@@ -1283,9 +1277,7 @@ static void gv11b_gr_intr_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc
gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f());
}
static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr)
static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc)
{
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
@@ -1460,9 +1452,7 @@ static void gv11b_gr_intr_report_icache_corrected_err(struct gk20a *g,
}
}
static void gv11b_gr_intr_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr)
static void gv11b_gr_intr_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc)
{
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
@@ -1559,24 +1549,22 @@ static void gv11b_gr_intr_handle_icache_exception(struct gk20a *g, u32 gpc, u32
}
void gv11b_gr_intr_handle_tpc_sm_ecc_exception(struct gk20a *g,
u32 gpc, u32 tpc,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr)
u32 gpc, u32 tpc)
{
/* Check for L1 tag ECC errors. */
gv11b_gr_intr_handle_l1_tag_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
gv11b_gr_intr_handle_l1_tag_exception(g, gpc, tpc);
/* Check for LRF ECC errors. */
gv11b_gr_intr_handle_lrf_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
gv11b_gr_intr_handle_lrf_exception(g, gpc, tpc);
/* Check for CBU ECC errors. */
gv11b_gr_intr_handle_cbu_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
gv11b_gr_intr_handle_cbu_exception(g, gpc, tpc);
/* Check for L1 data ECC errors. */
gv11b_gr_intr_handle_l1_data_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
gv11b_gr_intr_handle_l1_data_exception(g, gpc, tpc);
/* Check for L0 && L1 icache ECC errors. */
gv11b_gr_intr_handle_icache_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
gv11b_gr_intr_handle_icache_exception(g, gpc, tpc);
}
void gv11b_gr_intr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,

4
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -895,9 +895,7 @@ struct gpu_ops {
void (*flush_channel_tlb)(struct gk20a *g);
void (*set_hww_esr_report_mask)(struct gk20a *g);
void (*handle_tpc_sm_ecc_exception)(struct gk20a *g,
u32 gpc, u32 tpc,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr);
u32 gpc, u32 tpc);
void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel);
void (*clear_sm_hww)(struct gk20a *g, u32 gpc, u32 tpc,