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gpu: nvgpu: sim_pci: reconcile sim escape paths between RM and nvgpu

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SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM for dgpu.

Required for dgpu to work on NET23.

Bug 2539889
Bug 200582707

Change-Id: Ied05dae00928d44249df695429fb5029331f1286
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2256665
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Seshendra Gadagottu
2019-12-05 23:08:09 -08:00
committed by Alex Waterman
parent 53bd199e30
commit bf353cea6c
1 changed files with 5 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/common/sim/sim_pci.c
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@@ -177,14 +177,16 @@ static void nvgpu_sim_esc_readl(struct gk20a *g,
*pci_sim_msg_param(g, 0) = index;
*pci_sim_msg_param(g, 4) = sizeof(u32);
data_offset = round_up(pathlen + 1, sizeof(u32));
*pci_sim_msg_param(g, 8) = data_offset + 0xc;
strcpy((char *)pci_sim_msg_param(g, 0xc), path);
*pci_sim_msg_param(g, 8) = data_offset;
strcpy((char *)pci_sim_msg_param(g, sim_escape_read_hdr_size()), path);
err = pci_issue_rpc_and_wait(g);
if (err == 0) {
nvgpu_memcpy((u8 *)data,
(u8 *)pci_sim_msg_param(g, data_offset + 0xc),
(u8 *)pci_sim_msg_param(g,
nvgpu_safe_add_u32(data_offset,
sim_escape_read_hdr_size())),
sizeof(u32));
} else {
*data = 0xffffffff;