nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 01:50:07 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: g106 hal for mclk switching

Browse Source 
move mclk switching to gp106 hal.

Bug 1921082
JIRA EVLR-1269

Change-Id: I97812b871384460bec88fddac0f6a326df12fc45
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1499393
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2017-06-06 18:58:17 -07:00
committed by mobile promotions
parent 83f8bb225b
commit c32c86342e
6 changed files with 34 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/Makefile.nvgpu
View File

@@ -192,6 +192,7 @@ nvgpu-y += \
gp106/hal_gp106.o \ gp106/hal_gp106.o \
gp106/mm_gp106.o \ gp106/mm_gp106.o \
gp106/pmu_gp106.o \ gp106/pmu_gp106.o \
gp106/pmu_mclk_gp106.o \
gp106/gr_gp106.o \ gp106/gr_gp106.o \
gp106/gr_ctx_gp106.o \ gp106/gr_ctx_gp106.o \
gp106/acr_gp106.o \ gp106/acr_gp106.o \
@@ -200,7 +201,6 @@ nvgpu-y += \
gp106/ltc_gp106.o \ gp106/ltc_gp106.o \
gp106/fb_gp106.o \ gp106/fb_gp106.o \
gp106/regops_gp106.o \ gp106/regops_gp106.o \
clk/clk_mclk.o \
pstate/pstate.o \ pstate/pstate.o \
clk/clk_vin.o \ clk/clk_vin.o \
clk/clk_fll.o \ clk/clk_fll.o \

7
drivers/gpu/nvgpu/clk/clk_mclk.h
View File

@@ -21,9 +21,6 @@
#define GP106_MCLK_HIGH_SPEED 2 #define GP106_MCLK_HIGH_SPEED 2
#define GP106_MCLK_NUM_SPEED 3 #define GP106_MCLK_NUM_SPEED 3
#define GP106_MEM_CONFIG_GDDR5_PG418 0
#define GP106_MEM_CONFIG_GDDR5_PG419 1
enum gk20a_mclk_speed { enum gk20a_mclk_speed {
gk20a_mclk_low_speed, gk20a_mclk_low_speed,
gk20a_mclk_mid_speed, gk20a_mclk_mid_speed,
@@ -51,8 +48,4 @@ struct clk_mclk_state {
#endif #endif
}; };
int clk_mclkseq_init_mclk_gddr5(struct gk20a *g);
void clk_mclkseq_deinit_mclk_gddr5(struct gk20a *g);
int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val);
#endif #endif

1
drivers/gpu/nvgpu/common/linux/pci.c
View File

@@ -28,6 +28,7 @@
#include "clk/clk_mclk.h" #include "clk/clk_mclk.h"
#include "module.h" #include "module.h"
#include "intr.h" #include "intr.h"
#include "gp106/pmu_mclk_gp106.h"
#include "pci.h" #include "pci.h"

5
drivers/gpu/nvgpu/gp106/pmu_gp106.c
View File

@@ -19,6 +19,7 @@
#include "gm20b/pmu_gm20b.h" #include "gm20b/pmu_gm20b.h"
#include "gp10b/pmu_gp10b.h" #include "gp10b/pmu_gp10b.h"
#include "gp106/pmu_gp106.h" #include "gp106/pmu_gp106.h"
#include "gp106/pmu_mclk_gp106.h"
#include "gp106/acr_gp106.h" #include "gp106/acr_gp106.h"
#include "clk/clk_mclk.h" #include "clk/clk_mclk.h"
@@ -443,8 +444,8 @@ void gp106_init_pmu_ops(struct gpu_ops *gops)
gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
gops->pmu.dump_secure_fuses = NULL; gops->pmu.dump_secure_fuses = NULL;
gops->pmu.reset = gp106_falcon_reset; gops->pmu.reset = gp106_falcon_reset;
gops->pmu.mclk_init = clk_mclkseq_init_mclk_gddr5; gops->pmu.mclk_init = gp106_mclk_init;
gops->pmu.mclk_deinit = clk_mclkseq_deinit_mclk_gddr5; gops->pmu.mclk_deinit = gp106_mclk_deinit;
gops->pmu.is_pmu_supported = gp106_is_pmu_supported; gops->pmu.is_pmu_supported = gp106_is_pmu_supported;
gk20a_dbg_fn("done"); gk20a_dbg_fn("done");

9
drivers/gpu/nvgpu/clk/clk_mclk.c → drivers/gpu/nvgpu/gp106/pmu_mclk_gp106.c
View File

@@ -20,6 +20,7 @@
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
#include "gk20a/platform_gk20a.h" #include "gk20a/platform_gk20a.h"
#endif #endif
#include "gp106/pmu_mclk_gp106.h"
#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
#include <nvgpu/hw/gp106/hw_fb_gp106.h> #include <nvgpu/hw/gp106/hw_fb_gp106.h>
@@ -2689,7 +2690,7 @@ done:
return status; return status;
} }
void clk_mclkseq_deinit_mclk_gddr5(struct gk20a *g) void gp106_mclk_deinit(struct gk20a *g)
{ {
struct clk_mclk_state *mclk = &g->clk_pmu.clk_mclk; struct clk_mclk_state *mclk = &g->clk_pmu.clk_mclk;
@@ -2697,7 +2698,7 @@ void clk_mclkseq_deinit_mclk_gddr5(struct gk20a *g)
nvgpu_mutex_destroy(&mclk->mclk_lock); nvgpu_mutex_destroy(&mclk->mclk_lock);
} }
int clk_mclkseq_init_mclk_gddr5(struct gk20a *g) int gp106_mclk_init(struct gk20a *g)
{ {
struct clk_mclk_state *mclk; struct clk_mclk_state *mclk;
int status; int status;
@@ -2768,7 +2769,7 @@ int clk_mclkseq_init_mclk_gddr5(struct gk20a *g)
mclk->debugfs_set = true; mclk->debugfs_set = true;
} }
#endif #endif
g->ops.pmu.mclk_change = clk_mclkseq_change_mclk_gddr5; g->ops.pmu.mclk_change = gp106_mclk_change;
mclk->init = true; mclk->init = true;
@@ -2781,7 +2782,7 @@ fail_mclk_mutex:
return err; return err;
} }
int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) int gp106_mclk_change(struct gk20a *g, u16 val)
{ {
struct clk_mclk_state *mclk; struct clk_mclk_state *mclk;
struct pmu_payload payload; struct pmu_payload payload;

24
drivers/gpu/nvgpu/gp106/pmu_mclk_gp106.h Normal file
View File

@@ -0,0 +1,24 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _PMU_MCLK_GP106_H_
#define _PMU_MCLK_GP106_H_
#define GP106_MEM_CONFIG_GDDR5_PG418 0
#define GP106_MEM_CONFIG_GDDR5_PG419 1
extern int gp106_mclk_init(struct gk20a *g);
extern void gp106_mclk_deinit(struct gk20a *g);
extern int gp106_mclk_change(struct gk20a *g, u16 val);
#endif