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gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.ecc unit

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Fix CERT INT30-C erros in hal.gr.ecc units.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: I3811bfe0c542e7960ab8dbc2877465f7a72d1761
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133803
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-06-10 13:21:16 -07:00
committed by mobile promotions
parent fb0e627a25
commit c3c541b1af
1 changed files with 10 additions and 6 deletions
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16
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b.c
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@@ -90,7 +90,8 @@ int gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride;
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting GPCCS fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
@@ -147,8 +148,10 @@ int gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFF00U) >> 8U;
unsigned int tpc = (error_info & 0xFFU);
unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride
+ tpc * tpc_stride;
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_add_u32(
nvgpu_safe_mult_u32(gpc , gpc_stride),
nvgpu_safe_mult_u32(tpc , tpc_stride)));
nvgpu_info(g, "Injecting SM fault %s for gpc: %d, tpc: %d",
err->name, gpc, tpc);
@@ -182,7 +185,8 @@ int gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = err->get_reg_addr() + gpc * gpc_stride;
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting MMU fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
@@ -216,8 +220,8 @@ int gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
unsigned int gpc_stride = nvgpu_get_litter_value(g,
GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = err->get_reg_addr()
+ gpc * gpc_stride;
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting GCC fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));