gpu: nvgpu: add common.hal.gr.init unit

Add new HAL unit common.hal.gr.init with below source files
hal/gr/init/gr_init_gm20b.c
hal/gr/init/gr_init_gm20b.h

In gr_gk20a_init_golden_ctx_image() we force FE power mode on and also
disable it. Extract out this sequence into new unit and expose new HAL
operation that takes a boolean flag to enable/disable power mode

g->ops.gr.init.fe_pwr_mode_force_on()

Use new HAL operation in gr_gk20a_init_golden_ctx_image()
Set this HAL for all the chips

Jira NVGPU-2961

Change-Id: I1dd35d94fda5e5296af67c0abc944e200fb752ea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070607
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/enabled.h>
+
+#include "gr_init_gm20b.h"
+
+#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
+
+#define FE_PWR_MODE_TIMEOUT_MAX_US 2000U
+#define FE_PWR_MODE_TIMEOUT_DEFAULT_US 10U
+
+int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on)
+{
+	struct nvgpu_timeout timeout;
+	int ret = -ETIMEDOUT;
+	u32 reg_val;
+
+	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
+		return 0;
+	}
+
+	if (force_on) {
+		reg_val = gr_fe_pwr_mode_req_send_f() |
+			  gr_fe_pwr_mode_mode_force_on_f();
+	} else {
+		reg_val = gr_fe_pwr_mode_req_send_f() |
+			  gr_fe_pwr_mode_mode_auto_f();
+	}
+
+	nvgpu_timeout_init(g, &timeout,
+			   FE_PWR_MODE_TIMEOUT_MAX_US /
+				FE_PWR_MODE_TIMEOUT_DEFAULT_US,
+			   NVGPU_TIMER_RETRY_TIMER);
+
+	nvgpu_writel(g, gr_fe_pwr_mode_r(), reg_val);
+
+	do {
+		u32 req = gr_fe_pwr_mode_req_v(
+				nvgpu_readl(g, gr_fe_pwr_mode_r()));
+		if (req == gr_fe_pwr_mode_req_done_v()) {
+			ret = 0;
+			break;
+		}
+
+		nvgpu_udelay(FE_PWR_MODE_TIMEOUT_DEFAULT_US);
+	} while (nvgpu_timeout_expired_msg(&timeout,
+				"timeout setting FE mode %u", force_on) == 0);
+
+	return ret;
+}

drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_GR_INIT_GM20B_H
+#define NVGPU_GR_INIT_GM20B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on);
+
+#endif /* NVGPU_GR_INIT_GM20B_H */