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gpu: nvgpu: update FECS falcon base addr init

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FECS falcon base address was being set without invoking hal api. Remove
FALCON_FECS_BASE. This patch defines gpu_ops.gr.fecs_falcon_base_addr hal
api to get this base address.

JIRA NVGPU-1587

Change-Id: I9c8e60be4ee81a154020c982893725a12ebb72ef
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969430
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2018-12-10 13:49:18 +05:30
committed by mobile promotions
parent 84b493e644
commit c6fc301a9b
14 changed files with 24 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
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@@ -728,7 +728,7 @@ int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
flcn->is_interrupt_enabled = true;
break;
case FALCON_ID_FECS:
flcn->flcn_base = FALCON_FECS_BASE;
flcn->flcn_base = g->ops.gr.fecs_falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;

2
drivers/gpu/nvgpu/common/falcon/falcon_gp106.c
View File

@@ -71,7 +71,7 @@ int gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
flcn->is_interrupt_enabled = false;
break;
case FALCON_ID_FECS:
flcn->flcn_base = FALCON_FECS_BASE;
flcn->flcn_base = g->ops.gr.fecs_falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;

5
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -8681,3 +8681,8 @@ u32 gk20a_gr_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g)
{
return nvgpu_readl(g, gr_fecs_ctx_state_store_major_rev_id_r());
}
u32 gr_gk20a_fecs_falcon_base_addr(void)
{
return gr_fecs_irqsset_r();
}

1
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
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@@ -797,4 +797,5 @@ int gk20a_gr_alloc_ctx_buffer(struct gk20a *g,
void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr);
u32 gk20a_gr_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g);
u32 gr_gk20a_fecs_falcon_base_addr(void);
#endif /*__GR_GK20A_H__*/

1
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -233,6 +233,7 @@ static const struct gpu_ops gm20b_ops = {
.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = gr_gm20b_init_fs_state,
.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
.fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
.set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,

5
drivers/gpu/nvgpu/gp106/gr_gp106.c
View File

@@ -256,3 +256,8 @@ fail_free_preempt:
fail:
return err;
}
u32 gr_gp106_fecs_falcon_base_addr(void)
{
return gr_fecs_irqsset_r();
}

1
drivers/gpu/nvgpu/gp106/gr_gp106.h
View File

@@ -40,5 +40,6 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
struct vm_gk20a *vm, u32 class,
u32 graphics_preempt_mode,
u32 compute_preempt_mode);
u32 gr_gp106_fecs_falcon_base_addr(void);
#endif /* NVGPU_GR_GP106_H */

1
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -297,6 +297,7 @@ static const struct gpu_ops gp106_ops = {
.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = gr_gp10b_init_fs_state,
.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
.fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,

1
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -252,6 +252,7 @@ static const struct gpu_ops gp10b_ops = {
.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = gr_gp10b_init_fs_state,
.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
.fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -81,6 +81,7 @@
#include "gp106/sec2_gp106.h"
#include "gp106/bios_gp106.h"
#include "gp106/gr_gp106.h"
#include "gp10b/gr_gp10b.h"
#include "gp10b/ce_gp10b.h"
@@ -354,6 +355,7 @@ static const struct gpu_ops gv100_ops = {
.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = gr_gv11b_init_fs_state,
.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
.fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode,
.set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask,

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -305,6 +305,7 @@ static const struct gpu_ops gv11b_ops = {
.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = gr_gv11b_init_fs_state,
.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
.fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,

1
drivers/gpu/nvgpu/include/nvgpu/falcon.h
View File

@@ -42,7 +42,6 @@
/*
* Falcon Base address Defines
*/
#define FALCON_FECS_BASE 0x00409000U
#define FALCON_GPCCS_BASE 0x0041a000U
/* Falcon Register index */

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -622,6 +622,7 @@ struct gpu_ops {
void (*dump_ctxsw_stats)(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
} ctxsw_prog;
u32 (*fecs_falcon_base_addr)(void);
} gr;
struct {
void (*init_hw)(struct gk20a *g);

3
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -88,6 +88,8 @@
#include "gp106/sec2_gp106.h"
#include "gp106/bios_gp106.h"
#include "gp106/gr_gp106.h"
#include "gp10b/gr_gp10b.h"
#include "gp10b/ce_gp10b.h"
#include "gp10b/fifo_gp10b.h"
@@ -368,6 +370,7 @@ static const struct gpu_ops tu104_ops = {
.get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = gr_gv11b_init_fs_state,
.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
.fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode,
.set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask,