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gpu: nvgpu: add accessors for PMU bar0 status

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Add missing register host_err and bar0 error masks to find actual error
type of pmu bar0 pri timeout.

Jira NVGPU-1902

Change-Id: I4ec5a5230517e34bf5a843c2f0d9b0473875350f
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069182
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Prateek sethi
2019-03-10 20:21:31 +05:30
committed by mobile promotions
parent 3859725ea1
commit c990a3ee2b
7 changed files with 199 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -766,6 +766,30 @@ static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0U + i*4U;

30
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -814,10 +814,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
{
return 0x0010a988U;
}
static inline u32 pwr_pmu_bar0_host_error_r(void)
{
return 0x0010a990U;
}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0U + i*4U;

30
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -822,10 +822,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
{
return 0x0010a988U;
}
static inline u32 pwr_pmu_bar0_host_error_r(void)
{
return 0x0010a990U;
}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0U + i*4U;

30
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -818,10 +818,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
{
return 0x0010a988U;
}
static inline u32 pwr_pmu_bar0_host_error_r(void)
{
return 0x0010a990U;
}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0U + i*4U;

30
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -922,10 +922,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
{
return 0x0010a988U;
}
static inline u32 pwr_pmu_bar0_host_error_r(void)
{
return 0x0010a990U;
}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0U + i*4U;

30
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -978,10 +978,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
{
return 0x0010a988U;
}
static inline u32 pwr_pmu_bar0_host_error_r(void)
{
return 0x0010a990U;
}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0U + i*4U;

30
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pwr_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -922,10 +922,38 @@ static inline u32 pwr_pmu_bar0_fecs_error_r(void)
{
return 0x0010a988U;
}
static inline u32 pwr_pmu_bar0_host_error_r(void)
{
return 0x0010a990U;
}
static inline u32 pwr_pmu_bar0_error_status_r(void)
{
return 0x0010a7b0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_host_m(void)
{
return U32(0x1U) << 0U;
}
static inline u32 pwr_pmu_bar0_error_status_timeout_fecs_m(void)
{
return U32(0x1U) << 1U;
}
static inline u32 pwr_pmu_bar0_error_status_cmd_hwerr_m(void)
{
return U32(0x1U) << 2U;
}
static inline u32 pwr_pmu_bar0_error_status_err_cmd_m(void)
{
return U32(0x1U) << 3U;
}
static inline u32 pwr_pmu_bar0_error_status_hosterr_m(void)
{
return U32(0x1U) << 30U;
}
static inline u32 pwr_pmu_bar0_error_status_fecserr_m(void)
{
return U32(0x1U) << 31U;
}
static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
{
return 0x0010a6c0U + i*4U;