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gpu: nvgpu: cond. compilation of tegra dvfs code
Protect the code dependent on tegra dvfs and bpmp dvfs code under the config flags CONFIG_TEGRA_DVFS and CONFIG_NV_TEGRA_BPMP. Also, update clk_config_dvfs and clk_program_na_gpc_pll to handle the error value returned from g->ops.clk.predict_mv_at_hz_cur_tfloor. Bug 2834141 Change-Id: I124d29f22e59fd6af7801ca859c4470483c8f7d8 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306433 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
This commit is contained in:
committed by
Alex Waterman
parent
bf353cea6c
commit
cc043e1506
@@ -18,8 +18,14 @@
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#include <linux/clk.h>
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#ifdef CONFIG_TEGRA_DVFS
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#include <soc/tegra/tegra-dvfs.h>
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#endif /* CONFIG_TEGRA_DVFS */
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#ifdef CONFIG_NV_TEGRA_BPMP
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#include <soc/tegra/tegra-bpmp-dvfs.h>
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#endif /* CONFIG_NV_TEGRA_BPMP */
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#include <nvgpu/pmu/clk/clk.h>
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#include "clk.h"
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@@ -85,6 +91,7 @@ static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
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#ifdef CONFIG_TEGRA_DVFS
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/*
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* On Tegra platforms with GPCPLL bus (gbus) GPU tegra_clk clock exposed
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* to frequency governor is a shared user on the gbus. The latter can be
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@@ -93,10 +100,14 @@ static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
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if (g->clk.tegra_clk)
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return tegra_dvfs_get_fmax_at_vmin_safe_t(
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g->clk.tegra_clk_parent);
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#endif
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if (platform->maxmin_clk_id)
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if (platform->maxmin_clk_id) {
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#ifdef CONFIG_NV_TEGRA_BPMP
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return tegra_bpmp_dvfs_get_fmax_at_vmin(
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platform->maxmin_clk_id);
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#endif
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}
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return 0;
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}
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@@ -117,8 +128,12 @@ static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g)
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static int nvgpu_linux_predict_mv_at_hz_cur_tfloor(struct clk_gk20a *clk,
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unsigned long rate)
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{
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#ifdef CONFIG_TEGRA_DVFS
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return tegra_dvfs_predict_mv_at_hz_cur_tfloor(
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clk->tegra_clk_parent, rate);
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#else
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return -EINVAL;
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#endif
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}
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static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain)
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@@ -128,7 +143,11 @@ static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain)
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switch (api_domain) {
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case CTRL_CLK_DOMAIN_GPCCLK:
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#ifdef CONFIG_TEGRA_DVFS
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ret = tegra_dvfs_get_maxrate(g->clk.tegra_clk_parent);
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#else
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ret = 0;
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#endif
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/* If dvfs not supported */
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if (ret == 0) {
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int err = nvgpu_clk_arb_get_arbiter_clk_range(g,
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