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gpu: nvgpu: gv11b: Reorg pmu HAL init
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3f8a763a7bebf201c2242eecde7ff998aad07d0a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Sunny He
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@@ -32,19 +32,23 @@
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#include "gk20a/regops_gk20a.h"
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#include "gk20a/fb_gk20a.h"
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#include "gk20a/mm_gk20a.h"
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#include "gk20a/pmu_gk20a.h"
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#include "gm20b/ltc_gm20b.h"
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#include "gm20b/gr_gm20b.h"
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#include "gm20b/fifo_gm20b.h"
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#include "gm20b/fb_gm20b.h"
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#include "gm20b/mm_gm20b.h"
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#include "gm20b/pmu_gm20b.h"
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#include "gm20b/acr_gm20b.h"
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#include "gp10b/fb_gp10b.h"
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#include "gp106/clk_gp106.h"
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#include "gp106/clk_arb_gp106.h"
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#include "gp106/pmu_gp106.h"
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#include "gp106/acr_gp106.h"
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#include "gp106/sec2_gp106.h"
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#include "gm206/bios_gm206.h"
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#include "gp106/therm_gp106.h"
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#include "gp106/xve_gp106.h"
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@@ -58,6 +62,7 @@
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#include "gp10b/fifo_gp10b.h"
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#include "gp10b/fecs_trace_gp10b.h"
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#include "gp10b/mm_gp10b.h"
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#include "gp10b/pmu_gp10b.h"
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#include "gv11b/hal_gv11b.h"
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#include "gv11b/gr_gv11b.h"
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@@ -87,6 +92,7 @@
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#include <nvgpu/hw/gv100/hw_ram_gv100.h>
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#include <nvgpu/hw/gv100/hw_top_gv100.h>
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#include <nvgpu/hw/gv100/hw_pram_gv100.h>
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#include <nvgpu/hw/gv100/hw_pwr_gv100.h>
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static int gv100_get_litter_value(struct gk20a *g, int value)
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{
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@@ -345,6 +351,45 @@ static const struct gpu_ops gv100_ops = {
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.exit = gk20a_pramin_exit,
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.data032_r = pram_data032_r,
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},
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.pmu = {
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.init_wpr_region = gm20b_pmu_init_acr,
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.load_lsfalcon_ucode = gp106_load_falcon_ucode,
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.is_lazy_bootstrap = gp106_is_lazy_bootstrap,
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.is_priv_load = gp106_is_priv_load,
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.prepare_ucode = gp106_prepare_ucode_blob,
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.pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn,
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.get_wpr = gp106_wpr_info,
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.alloc_blob_space = gp106_alloc_blob_space,
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.pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg,
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.flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc,
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.falcon_wait_for_halt = sec2_wait_for_halt,
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.falcon_clear_halt_interrupt_status =
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sec2_clear_halt_interrupt_status,
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.init_falcon_setup_hw = init_sec2_setup_hw1,
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.pmu_queue_tail = gk20a_pmu_queue_tail,
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.pmu_get_queue_head = pwr_pmu_queue_head_r,
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.pmu_mutex_release = gk20a_pmu_mutex_release,
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.is_pmu_supported = gp106_is_pmu_supported,
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.pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list,
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.pmu_elpg_statistics = gp106_pmu_elpg_statistics,
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.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
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.pmu_is_lpwr_feature_supported =
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gp106_pmu_is_lpwr_feature_supported,
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.pmu_msgq_tail = gk20a_pmu_msgq_tail,
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.pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list,
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.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
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.pmu_queue_head = gk20a_pmu_queue_head,
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.pmu_pg_param_post_init = nvgpu_lpwr_post_init,
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.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
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.pmu_pg_init_param = gp106_pg_param_init,
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.reset_engine = gp106_pmu_engine_reset,
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.pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg,
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.write_dmatrfbase = gp10b_write_dmatrfbase,
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.pmu_mutex_size = pwr_pmu_mutex__size_1_v,
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.is_engine_in_reset = gp106_pmu_is_engine_in_reset,
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.pmu_get_queue_tail = pwr_pmu_queue_tail_r,
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.pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg,
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},
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.clk = {
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.init_clk_support = gp106_init_clk_support,
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.get_crystal_clk_hz = gp106_crystal_clk_hz,
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@@ -444,6 +489,7 @@ int gv100_init_hal(struct gk20a *g)
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gops->fecs_trace = gv100_ops.fecs_trace;
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gops->pramin = gv100_ops.pramin;
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gops->therm = gv100_ops.therm;
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gops->pmu = gv100_ops.pmu;
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gops->mc = gv100_ops.mc;
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gops->debug = gv100_ops.debug;
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gops->dbg_session_ops = gv100_ops.dbg_session_ops;
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@@ -470,13 +516,14 @@ int gv100_init_hal(struct gk20a *g)
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__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
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__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
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__nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
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/* for now */
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__nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
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g->pmu_lsf_pmu_wpr_init_done = 0;
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g->bootstrap_owner = LSF_FALCON_ID_SEC2;
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gv11b_init_gr(g);
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gp106_init_pmu_ops(g);
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gv11b_init_uncompressed_kind_map();
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gv11b_init_kind_attr();
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@@ -31,12 +31,15 @@
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#include "gk20a/flcn_gk20a.h"
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#include "gk20a/regops_gk20a.h"
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#include "gk20a/fb_gk20a.h"
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#include "gk20a/pmu_gk20a.h"
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#include "gm20b/ltc_gm20b.h"
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#include "gm20b/gr_gm20b.h"
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#include "gm20b/fb_gm20b.h"
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#include "gm20b/fifo_gm20b.h"
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#include "gm20b/mm_gm20b.h"
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#include "gm20b/acr_gm20b.h"
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#include "gm20b/pmu_gm20b.h"
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#include "gp10b/ltc_gp10b.h"
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#include "gp10b/therm_gp10b.h"
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@@ -47,6 +50,9 @@
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#include "gp10b/fecs_trace_gp10b.h"
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#include "gp10b/fb_gp10b.h"
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#include "gp10b/mm_gp10b.h"
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#include "gp10b/pmu_gp10b.h"
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#include "gp106/pmu_gp106.h"
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#include "hal_gv11b.h"
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#include "gr_gv11b.h"
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@@ -70,6 +76,7 @@
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#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
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#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
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#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
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#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
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static int gv11b_get_litter_value(struct gk20a *g, int value)
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{
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@@ -368,6 +375,30 @@ static const struct gpu_ops gv11b_ops = {
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.init_therm_setup_hw = gp10b_init_therm_setup_hw,
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.elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
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},
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.pmu = {
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.pmu_setup_elpg = gp10b_pmu_setup_elpg,
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.pmu_get_queue_head = pwr_pmu_queue_head_r,
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.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
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.pmu_get_queue_tail = pwr_pmu_queue_tail_r,
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.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
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.pmu_queue_head = gk20a_pmu_queue_head,
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.pmu_queue_tail = gk20a_pmu_queue_tail,
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.pmu_msgq_tail = gk20a_pmu_msgq_tail,
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.pmu_mutex_size = pwr_pmu_mutex__size_1_v,
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.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
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.pmu_mutex_release = gk20a_pmu_mutex_release,
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.write_dmatrfbase = gp10b_write_dmatrfbase,
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.pmu_elpg_statistics = gp106_pmu_elpg_statistics,
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.pmu_pg_init_param = gv11b_pg_gr_init,
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.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
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.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
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.dump_secure_fuses = pmu_dump_security_fuses_gp10b,
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.reset_engine = gp106_pmu_engine_reset,
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.is_engine_in_reset = gp106_pmu_is_engine_in_reset,
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.pmu_nsbootstrap = gv11b_pmu_bootstrap,
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.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
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.is_pmu_supported = gv11b_is_pmu_supported,
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},
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.regops = {
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.get_global_whitelist_ranges =
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gv11b_get_global_whitelist_ranges,
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@@ -463,6 +494,7 @@ int gv11b_init_hal(struct gk20a *g)
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gops->mm = gv11b_ops.mm;
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gops->fecs_trace = gv11b_ops.fecs_trace;
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gops->therm = gv11b_ops.therm;
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gops->pmu = gv11b_ops.pmu;
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gops->regops = gv11b_ops.regops;
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gops->mc = gv11b_ops.mc;
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gops->debug = gv11b_ops.debug;
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@@ -479,13 +511,44 @@ int gv11b_init_hal(struct gk20a *g)
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gv11b_ops.chip_init_gpu_characteristics;
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gops->get_litter_value = gv11b_ops.get_litter_value;
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/* boot in non-secure modes for time beeing */
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/* boot in non-secure modes for time being */
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__nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
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__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
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__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
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/* priv security dependent ops */
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if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
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/* Add in ops from gm20b acr */
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gops->pmu.prepare_ucode = prepare_ucode_blob,
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gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn,
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gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
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gops->pmu.is_priv_load = gm20b_is_priv_load,
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gops->pmu.get_wpr = gm20b_wpr_info,
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gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
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gops->pmu.pmu_populate_loader_cfg =
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gm20b_pmu_populate_loader_cfg,
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gops->pmu.flcn_populate_bl_dmem_desc =
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gm20b_flcn_populate_bl_dmem_desc,
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gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
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gops->pmu.falcon_clear_halt_interrupt_status =
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clear_halt_interrupt_status,
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gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1,
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gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
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gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
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gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
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gops->pmu.is_priv_load = gp10b_is_priv_load;
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} else {
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/* Inherit from gk20a */
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gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
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gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
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gops->pmu.load_lsfalcon_ucode = NULL;
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gops->pmu.init_wpr_region = NULL;
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gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
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}
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gv11b_init_gr(g);
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gv11b_init_pmu_ops(g);
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gv11b_init_uncompressed_kind_map();
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gv11b_init_kind_attr();
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@@ -36,12 +36,12 @@
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#define ALIGN_4KB 12
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static bool gv11b_is_pmu_supported(struct gk20a *g)
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bool gv11b_is_pmu_supported(struct gk20a *g)
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{
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return true;
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}
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static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
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int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
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{
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struct gk20a *g = gk20a_from_pmu(pmu);
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struct mm_gk20a *mm = &g->mm;
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@@ -178,7 +178,7 @@ static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg,
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msg->msg.pg.msg_type);
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}
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static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
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int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct pmu_cmd cmd;
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@@ -206,7 +206,7 @@ static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
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return 0;
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}
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static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
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int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct pmu_cmd cmd;
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@@ -234,27 +234,3 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
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return 0;
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}
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void gv11b_init_pmu_ops(struct gk20a *g)
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{
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struct gpu_ops *gops = &g->ops;
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gp10b_init_pmu_ops(g);
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gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap;
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gops->pmu.is_pmu_supported = gv11b_is_pmu_supported;
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gops->pmu.reset_engine = gp106_pmu_engine_reset;
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gops->pmu.is_engine_in_reset = gp106_pmu_is_engine_in_reset;
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gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r;
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gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v;
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gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r;
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gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v;
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gops->pmu.pmu_queue_head = gk20a_pmu_queue_head;
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gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail;
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gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire;
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gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release;
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gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail;
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gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v;
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gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics;
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gops->pmu.pmu_pg_init_param = gv11b_pg_gr_init;
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gops->pmu.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask;
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}
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@@ -18,6 +18,9 @@
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struct gk20a;
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void gv11b_init_pmu_ops(struct gk20a *g);
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bool gv11b_is_pmu_supported(struct gk20a *g);
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int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu);
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int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id);
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int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id);
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#endif /*__PMU_GV11B_H_*/
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