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gpu: nvgpu: split pmu_gv11b fusa/non-fusa hal
gv11b_pmu_inject_ecc_error is needed in fusa functions. Hence moved it to pmu_gv11b_fusa.c. Moved compilation of pmu_gv11b.c under NON_FUSA and updated the arch. JIRA NVGPU-3690 Change-Id: I88488591a72b8e43eccba44fc2afe4d0b5973a1c Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2156875 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -39,15 +39,6 @@
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#define ALIGN_4KB 12
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int gv11b_pmu_inject_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info)
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{
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nvgpu_info(g, "Injecting PMU fault %s", err->name);
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nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
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return 0;
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}
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#ifdef CONFIG_NVGPU_LS_PMU
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/* PROD settings for ELPG sequencing registers*/
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static struct pg_init_sequence_list _pginitseq_gv11b[] = {
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@@ -39,6 +39,15 @@
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#define ALIGN_4KB 12
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int gv11b_pmu_inject_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info)
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{
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nvgpu_info(g, "Injecting PMU fault %s", err->name);
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nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
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return 0;
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}
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static inline u32 pmu_falcon_ecc_control_r(void)
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{
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return pwr_pmu_falcon_ecc_control_r();
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