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gpu: nvgpu: Add engine reset profiling

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This is a key part of the fifo recovery sequence.

JIRA NVGPU-5606

Change-Id: I8807884394834b912f25d7c535ee22f547988b2d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2382590
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Alex Waterman
2020-07-20 11:04:22 -05:00
parent 1bcdc306a0
commit d0714b40c1
5 changed files with 50 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -43,6 +43,9 @@
#include <nvgpu/fifo.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/gops_mc.h>
#include <nvgpu/swprofile.h>
#include <nvgpu/fifo/swprofile.h>
#define FECS_METHOD_WFI_RESTORE 0x80000U
@@ -551,6 +554,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
{
enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL;
struct nvgpu_engine_info *engine_info;
struct nvgpu_swprofiler *prof = &g->fifo.eng_reset_profiler;
nvgpu_log_fn(g, " ");
@@ -558,6 +562,8 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
return;
}
nvgpu_swprofile_begin_sample(prof);
engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
if (engine_info != NULL) {
@@ -568,12 +574,15 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
nvgpu_err(g, "unsupported engine_id %d", engine_id);
}
nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_PREAMBLE);
if (engine_enum == NVGPU_ENGINE_GR) {
#ifdef CONFIG_NVGPU_POWER_PG
if (nvgpu_pg_elpg_disable(g) != 0 ) {
nvgpu_err(g, "failed to set disable elpg");
}
#endif
nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_ELPG_DISABLE);
#ifdef CONFIG_NVGPU_FECS_TRACE
/*
@@ -586,6 +595,9 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
}
}
#endif
nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_FECS_TRACE_RESET);
if (!nvgpu_platform_is_simulation(g)) {
int err = 0;
@@ -596,6 +608,8 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
nvgpu_err(g, "failed to halt gr pipe");
}
nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_HALT_PIPELINE);
/*
* resetting engine using mc_enable_r() is not
* enough, we do full init sequence
@@ -606,6 +620,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
if (err != 0) {
nvgpu_err(g, "failed to reset gr engine");
}
nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_GR_RESET);
} else {
nvgpu_log(g, gpu_dbg_info,
"HALT gr pipe not supported and "
@@ -619,6 +634,8 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
#endif
}
nvgpu_swprofile_snapshot(prof, PROF_ENG_RESET_ELPG_REENABLE);
if ((engine_enum == NVGPU_ENGINE_GRCE) ||
(engine_enum == NVGPU_ENGINE_ASYNC_CE)) {
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)

7
drivers/gpu/nvgpu/common/fifo/fifo.c
View File

@@ -46,6 +46,10 @@ static const char *nvgpu_fifo_recovery_profile_events[] = {
NVGPU_FIFO_RECOVERY_PROFILE_EVENTS,
};
static const char *nvgpu_fifo_engine_reset_events[] = {
NVGPU_FIFO_ENGINE_RESET_EVENTS,
};
void nvgpu_fifo_cleanup_sw_common(struct gk20a *g)
{
struct nvgpu_fifo *f = &g->fifo;
@@ -107,6 +111,9 @@ int nvgpu_fifo_setup_sw_common(struct gk20a *g)
nvgpu_fifo_kickoff_profile_events);
nvgpu_swprofile_initialize(g, &f->recovery_profiler,
nvgpu_fifo_recovery_profile_events);
nvgpu_swprofile_initialize(g, &f->eng_reset_profiler,
nvgpu_fifo_engine_reset_events);
err = nvgpu_channel_setup_sw(g);
if (err != 0) {