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gpu: nvgpu: vgpu: remove cmd CHANNEL_BIND_GR_CTX

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Since gr_ctx has been moved to tsg, channel bind gr_ctx does nothing on
RM server.

Jira GVSCI-179

Change-Id: I80025c66beb943e0fe0e4cbb84db1b16d3b34b5b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1977575
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2018-12-20 15:03:28 -08:00
committed by mobile promotions
parent e768a5b2ca
commit d37187f1f8
2 changed files with 0 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
View File

@@ -87,7 +87,6 @@ enum {
TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47,
TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48,
TEGRA_VGPU_CMD_GR_CTX_FREE = 49,
TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX = 50,
TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51,
TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52,
TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53,
@@ -404,11 +403,6 @@ struct tegra_vgpu_gr_ctx_params {
u32 tsg_id;
};
struct tegra_vgpu_channel_bind_gr_ctx_params {
u64 ch_handle;
u64 gr_ctx_handle;
};
struct tegra_vgpu_tsg_bind_gr_ctx_params {
u32 tsg_id;
u64 gr_ctx_handle;
@@ -661,7 +655,6 @@ struct tegra_vgpu_cmd_msg {
struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode;
struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx;
struct tegra_vgpu_gr_ctx_params gr_ctx;
struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx;
struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx;
struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel;
struct tegra_vgpu_tsg_open_rel_params tsg_open;

38
drivers/gpu/nvgpu/vgpu/gr_vgpu.c
View File

@@ -450,32 +450,6 @@ void vgpu_gr_free_gr_ctx(struct gk20a *g,
}
}
static int vgpu_gr_ch_bind_gr_ctx(struct channel_gk20a *c)
{
struct tsg_gk20a *tsg;
struct nvgpu_gr_ctx *gr_ctx;
struct tegra_vgpu_cmd_msg msg = {0};
struct tegra_vgpu_channel_bind_gr_ctx_params *p =
&msg.params.ch_bind_gr_ctx;
int err;
tsg = tsg_gk20a_from_ch(c);
if (!tsg)
return -EINVAL;
gr_ctx = tsg->gr_ctx;
msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX;
msg.handle = vgpu_get_handle(c->g);
p->ch_handle = c->virt_ctx;
p->gr_ctx_handle = gr_ctx->virt_ctx;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
WARN_ON(err);
return err;
}
static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg)
{
struct nvgpu_gr_ctx *gr_ctx = tsg->gr_ctx;
@@ -543,12 +517,6 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
goto out;
}
err = vgpu_gr_ch_bind_gr_ctx(c);
if (err) {
nvgpu_err(g, "fail to bind gr ctx buffer");
goto out;
}
/* allocate patch buffer */
err = vgpu_gr_alloc_channel_patch_ctx(g, c);
if (err) {
@@ -589,12 +557,6 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
goto out;
}
} else {
err = vgpu_gr_ch_bind_gr_ctx(c);
if (err) {
nvgpu_err(g, "fail to bind gr ctx buffer");
goto out;
}
/* commit gr ctx buffer */
err = g->ops.gr.commit_inst(c, gr_ctx->mem.gpu_va);
if (err) {