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gpu: nvgpu: do not writel_check zbc broadcast regs

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Use nvgpu_writel() instead of nvgpu_writel_check() for writing the zbc
color, depth and stencil values in L2 ZBC registers. Checking that the
read value equals is not sensible for broadcast registers, and in these
cases it's not necessary to read back the regs to synchronize memory.

Bug 2976632

Change-Id: Id40e7d0f435bae5a395b5553c186fc50302f7dea
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2345877
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Hölttä
2020-05-18 08:46:36 +03:00
committed by Alex Waterman
parent 91af7efd23
commit d5b14a389e
2 changed files with 8 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
View File

@@ -122,14 +122,13 @@ void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
{
u32 i;
nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
ltc_ltcs_ltss_dstg_zbc_index_address_f(
nvgpu_safe_add_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE)));
for (i = 0;
i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) {
nvgpu_writel_check(g,
ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
color_l2[i]);
}
}
@@ -141,13 +140,12 @@ void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
u32 depth_val,
u32 index)
{
nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
ltc_ltcs_ltss_dstg_zbc_index_address_f(
nvgpu_safe_add_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE)));
nvgpu_writel_check(g,
ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
depth_val);
nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
depth_val);
}
u32 gm20b_ltc_zbc_table_size(struct gk20a *g)

7
drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c
View File

@@ -42,13 +42,12 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
u32 stencil_depth,
u32 index)
{
nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
ltc_ltcs_ltss_dstg_zbc_index_address_f(
nvgpu_safe_add_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE)));
nvgpu_writel_check(g,
ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
stencil_depth);
nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
stencil_depth);
}
#endif /* CONFIG_NVGPU_GRAPHICS */