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gpu: nvgpu: rename enable/disable sched

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Rename
gk20a_tsg_enable_sched -> nvgpu_tsg_enable_sched
gk20a_tsg_disable_sched -> nvgpu_tsg_disable_sched

JIRA NVGPU-3144

Change-Id: I569025ea96e64b2bf3f8216a6080a8496570acf3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101277
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-04-19 10:58:50 -07:00
committed by mobile promotions
parent bdfc26af8b
commit df831c200b
4 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -557,14 +557,14 @@ u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg)
return tsg->timeslice_us;
}
void gk20a_tsg_enable_sched(struct gk20a *g, struct tsg_gk20a *tsg)
void nvgpu_tsg_enable_sched(struct gk20a *g, struct tsg_gk20a *tsg)
{
gk20a_fifo_set_runlist_state(g, BIT32(tsg->runlist_id),
RUNLIST_ENABLED);
}
void gk20a_tsg_disable_sched(struct gk20a *g, struct tsg_gk20a *tsg)
void nvgpu_tsg_disable_sched(struct gk20a *g, struct tsg_gk20a *tsg)
{
gk20a_fifo_set_runlist_state(g, BIT32(tsg->runlist_id),
RUNLIST_DISABLED);

4
drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c
View File

@@ -433,7 +433,7 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg)
nvgpu_mutex_acquire(&f->runlist_info[runlist_id]->runlist_lock);
/* WAR for Bug 2065990 */
gk20a_tsg_disable_sched(g, tsg);
nvgpu_tsg_disable_sched(g, tsg);
mutex_ret = nvgpu_pmu_lock_acquire(g, &g->pmu,
PMU_MUTEX_ID_FIFO, &token);
@@ -450,7 +450,7 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg)
}
/* WAR for Bug 2065990 */
gk20a_tsg_enable_sched(g, tsg);
nvgpu_tsg_enable_sched(g, tsg);
nvgpu_mutex_release(&f->runlist_info[runlist_id]->runlist_lock);

4
drivers/gpu/nvgpu/hal/fifo/tsg_gk20a.c
View File

@@ -32,7 +32,7 @@ void gk20a_tsg_enable(struct tsg_gk20a *tsg)
struct gk20a *g = tsg->g;
struct channel_gk20a *ch;
gk20a_tsg_disable_sched(g, tsg);
nvgpu_tsg_disable_sched(g, tsg);
/*
* Due to h/w bug that exists in Maxwell and Pascal,
@@ -63,5 +63,5 @@ void gk20a_tsg_enable(struct tsg_gk20a *tsg)
}
nvgpu_rwsem_up_read(&tsg->ch_list_lock);
gk20a_tsg_enable_sched(g, tsg);
nvgpu_tsg_enable_sched(g, tsg);
}

4
drivers/gpu/nvgpu/include/nvgpu/tsg.h
View File

@@ -117,8 +117,8 @@ bool nvgpu_tsg_check_ctxsw_timeout(struct tsg_gk20a *tsg,
int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level);
int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg);
void gk20a_tsg_enable_sched(struct gk20a *g, struct tsg_gk20a *tsg);
void gk20a_tsg_disable_sched(struct gk20a *g, struct tsg_gk20a *tsg);
void nvgpu_tsg_enable_sched(struct gk20a *g, struct tsg_gk20a *tsg);
void nvgpu_tsg_disable_sched(struct gk20a *g, struct tsg_gk20a *tsg);
int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg,
u32 priority);
int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g,