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gpu: nvgpu: fix active fbpa mask calculation

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In gr_gv100_get_active_fpba_mask(), we currently use num_fbpas passed by the
caller which is usually litter (max possible on h/w) value

We should instead read the number of FBPAs from h/w instead of reading litter
value

Jira NVGPUT-117

Change-Id: I6ecd4db0fd939e1dfebf31d27e0022ae02809399
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762721
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-06-27 13:50:42 +05:30
committed by mobile promotions
parent c7e1f6fe94
commit e1161fe0e4
2 changed files with 16 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/gv100/gr_gv100.c
View File

@@ -37,6 +37,7 @@
#include <nvgpu/hw/gv100/hw_fb_gv100.h>
#include <nvgpu/hw/gv100/hw_proj_gv100.h>
#include <nvgpu/hw/gv100/hw_fuse_gv100.h>
#include <nvgpu/hw/gv100/hw_top_gv100.h>
/*
@@ -371,9 +372,13 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g)
return size;
}
static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g, u32 num_fbpas)
static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g)
{
u32 active_fbpa_mask;
u32 num_fbpas, val;
val = nvgpu_readl(g, top_num_fbpas_r());
num_fbpas = top_num_fbpas_value_v(val);
/*
* Read active fbpa mask from fuse
@@ -404,7 +409,7 @@ int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g,
if ((cnt + (regs->count * num_fbpas)) > max_cnt)
return -EINVAL;
active_fbpa_mask = gr_gv100_get_active_fpba_mask(g, num_fbpas);
active_fbpa_mask = gr_gv100_get_active_fpba_mask(g);
for (idx = 0; idx < regs->count; idx++) {
for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) {
@@ -439,7 +444,7 @@ void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr,
u32 active_fbpa_mask;
u32 fbpa_id;
active_fbpa_mask = gr_gv100_get_active_fpba_mask(g, num_fbpas);
active_fbpa_mask = gr_gv100_get_active_fpba_mask(g);
for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) {
if (active_fbpa_mask & BIT(fbpa_id)) {

8
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
View File

@@ -80,6 +80,14 @@ static inline u32 top_num_fbps_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_num_fbpas_r(void)
{
return 0x0002243cU;
}
static inline u32 top_num_fbpas_value_v(u32 r)
{
return (r >> 0U) & 0x1fU;
}
static inline u32 top_ltc_per_fbp_r(void)
{
return 0x00022450U;