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gpu: nvgpu: move cg_enable after pmu_init is complete
This patch help resolve the boot time failures happening with pmu_exterr for porg. cg_enable can race with pmu_init thread, cg_enable is moved post pmu init thread to avoid the above race. Bug 200565050 Change-Id: I2192053eff8767847ea012ca20b3607d2f6cd26f Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2239959 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -526,6 +526,13 @@ static int nvgpu_pg_init_task(void *arg)
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nvgpu_pmu_dbg(g, "loaded zbc");
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pmu_setup_hw_enable_elpg(g);
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nvgpu_pmu_dbg(g, "PMU booted, thread exiting");
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gk20a_gr_wait_initialized(g);
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nvgpu_cg_blcg_enable_no_wait(g);
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nvgpu_cg_elcg_enable_no_wait(g);
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return 0;
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default:
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nvgpu_pmu_dbg(g, "invalid state");
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -84,6 +84,34 @@ void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g)
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_disable_no_wait(struct gk20a *g) {
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (g->blcg_enabled) {
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nvgpu_cg_set_mode(g, BLCG_MODE, BLCG_RUN);
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}
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_blcg_enable_no_wait(struct gk20a *g) {
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nvgpu_log_fn(g, " ");
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if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
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return;
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}
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nvgpu_mutex_acquire(&g->cg_pg_lock);
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if (g->blcg_enabled) {
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nvgpu_cg_set_mode(g, BLCG_MODE, BLCG_AUTO);
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}
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nvgpu_mutex_release(&g->cg_pg_lock);
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}
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void nvgpu_cg_elcg_enable(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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@@ -1,7 +1,7 @@
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/*
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* GK20A Graphics
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*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -4692,6 +4692,9 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
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/* Disable elcg until it gets enabled later in the init*/
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nvgpu_cg_elcg_disable_no_wait(g);
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/* Disable blcg until it gets enabled later in the init*/
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nvgpu_cg_blcg_disable_no_wait(g);
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/* enable fifo access */
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gk20a_writel(g, gr_gpfifo_ctl_r(),
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gr_gpfifo_ctl_access_enabled_f() |
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@@ -5012,7 +5015,6 @@ int gk20a_init_gr_support(struct gk20a *g)
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}
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}
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nvgpu_cg_elcg_enable_no_wait(g);
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/* GR is inialized, signal possible waiters */
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g->gr.initialized = true;
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nvgpu_cond_signal(&g->gr.init_wq);
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@@ -5159,6 +5161,7 @@ int gk20a_gr_reset(struct gk20a *g)
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nvgpu_cg_init_gr_load_gating_prod(g);
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nvgpu_cg_elcg_enable_no_wait(g);
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nvgpu_cg_blcg_enable_no_wait(g);
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/* GR is inialized, signal possible waiters */
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g->gr.initialized = true;
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -35,6 +35,8 @@ void nvgpu_cg_elcg_disable(struct gk20a *g);
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void nvgpu_cg_elcg_enable_no_wait(struct gk20a *g);
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void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g);
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void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable);
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void nvgpu_cg_blcg_disable_no_wait(struct gk20a *g);
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void nvgpu_cg_blcg_enable_no_wait(struct gk20a *g);
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void nvgpu_cg_blcg_mode_enable(struct gk20a *g);
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void nvgpu_cg_blcg_mode_disable(struct gk20a *g);
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