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gpu: nvgpu: func to set a value at hw semaphore addr

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Add a function to set a value to the hw_sema addr offset.
This will be used by the semaphore based gpfifo tracking.

JIRA NVGPU-9588

Change-Id: I719196907b86723d22c0cda49b0612f0810ec9ef
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898140
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ramalingam C
2023-05-03 18:46:38 +00:00
committed by mobile promotions
parent be5312cb9b
commit e46c1d2e10
2 changed files with 11 additions and 2 deletions
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10
drivers/gpu/nvgpu/common/semaphore/semaphore_hw.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -151,6 +151,14 @@ bool nvgpu_hw_semaphore_reset(struct nvgpu_hw_semaphore *hw_sema)
return true; return true;
} }
void nvgpu_hw_semaphore_set(struct nvgpu_hw_semaphore *hw_sema, u32 val)
{
struct nvgpu_semaphore_pool *pool = hw_sema->location.pool;
struct gk20a *g = pool->sema_sea->gk20a;
nvgpu_mem_wr(g, &pool->rw_mem, hw_sema->location.offset, val);
}
int nvgpu_hw_semaphore_read_next(struct nvgpu_hw_semaphore *hw_sema) int nvgpu_hw_semaphore_read_next(struct nvgpu_hw_semaphore *hw_sema)
{ {
return nvgpu_atomic_read(&hw_sema->next_value); return nvgpu_atomic_read(&hw_sema->next_value);

3
drivers/gpu/nvgpu/include/nvgpu/semaphore.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -76,6 +76,7 @@ void nvgpu_hw_semaphore_free(struct nvgpu_hw_semaphore *hw_sema);
u64 nvgpu_hw_semaphore_addr(struct nvgpu_hw_semaphore *hw_sema); u64 nvgpu_hw_semaphore_addr(struct nvgpu_hw_semaphore *hw_sema);
u32 nvgpu_hw_semaphore_read(struct nvgpu_hw_semaphore *hw_sema); u32 nvgpu_hw_semaphore_read(struct nvgpu_hw_semaphore *hw_sema);
bool nvgpu_hw_semaphore_reset(struct nvgpu_hw_semaphore *hw_sema); bool nvgpu_hw_semaphore_reset(struct nvgpu_hw_semaphore *hw_sema);
void nvgpu_hw_semaphore_set(struct nvgpu_hw_semaphore *hw_sema, u32 val);
int nvgpu_hw_semaphore_read_next(struct nvgpu_hw_semaphore *hw_sema); int nvgpu_hw_semaphore_read_next(struct nvgpu_hw_semaphore *hw_sema);
int nvgpu_hw_semaphore_update_next(struct nvgpu_hw_semaphore *hw_sema); int nvgpu_hw_semaphore_update_next(struct nvgpu_hw_semaphore *hw_sema);