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gpu: nvgpu: tsg MISRA fixes for Rule 10.8

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roundup() violates MISRA Rule 10.8 when using operands
of different sizes. Use u32 operands.

Jira NVGPU-3259

Change-Id: Iff8983347cfef0d63fc6a51c2df1b2798eba48f9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111434
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-05-03 11:18:41 -07:00
committed by mobile promotions
parent 5b1b2b98aa
commit e61452ab5c
1 changed files with 4 additions and 3 deletions
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7
drivers/gpu/nvgpu/hal/fifo/tsg_gv11b.c
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@@ -101,13 +101,14 @@ void gv11b_tsg_bind_channel_eng_method_buffers(struct tsg_gk20a *tsg,
g->ops.ramin.set_eng_method_buffer(g, &ch->inst_block, gpu_va);
}
static unsigned int gv11b_tsg_get_eng_method_buffer_size(struct gk20a *g)
static u32 gv11b_tsg_get_eng_method_buffer_size(struct gk20a *g)
{
unsigned int buffer_size;
u32 buffer_size;
u32 page_size = U32(PAGE_SIZE);
buffer_size = ((9U + 1U + 3U) * g->ops.ce.get_num_pce(g)) + 2U;
buffer_size = (27U * 5U * buffer_size);
buffer_size = roundup(buffer_size, PAGE_SIZE);
buffer_size = roundup(buffer_size, page_size);
nvgpu_log_info(g, "method buffer size in bytes %d", buffer_size);
return buffer_size;