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gpu: nvgpu: channel MISRA fix for Rule 10.1

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JIRA NVGPU-3388

Change-Id: I11b287239a36eaab5582428eb0d209520d0f286a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114871
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-05-08 11:29:51 -07:00
committed by mobile promotions
parent 9e63b64cd0
commit e6a8e63bb6
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/nvgpu/common/fifo/channel.c
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@@ -1027,7 +1027,7 @@ bool channel_gk20a_joblist_is_empty(struct nvgpu_channel *c)
if (channel_gk20a_is_prealloc_enabled(c)) {
u32 get = c->joblist.pre_alloc.get;
u32 put = c->joblist.pre_alloc.put;
return !(CIRC_CNT(put, get, c->joblist.pre_alloc.length));
return (CIRC_CNT(put, get, c->joblist.pre_alloc.length) == 0U);
}
return nvgpu_list_empty(&c->joblist.dynamic.jobs);