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gpu: nvgpu: prepare sec2 msg, allocator units

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SEC2 message handling unit can't be part of command handling unit as it
creates circular dependencies with the SEC2 tasks (ACR bootstrap)
SEC2 allocator unit shall encompass DMEM allocator and other allocators
used by SEC2.

JIRA NVGPU-2075

Change-Id: Ic2b8204d8225f2056785f035cbecdb776a9ecfe9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085749
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-03-29 07:03:02 +05:30
committed by mobile promotions
parent eef3ef7773
commit e848e9dfb8
13 changed files with 322 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/Makefile
View File

@@ -448,7 +448,9 @@ nvgpu-y += \
common/engine_queues/engine_fb_queue.o \
common/init/hal_init.o \
common/sec2/sec2.o \
common/sec2/sec2_allocator.o \
common/sec2/sec2_ipc.o \
common/sec2/sec2_msg.o \
common/sec2/sec2_queue.o \
common/sec2/sec2_seq.o \
common/io/io.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -160,7 +160,9 @@ srcs += common/sim.c \
common/acr/acr_sw_gv11b.c \
common/acr/acr_sw_tu104.c \
common/sec2/sec2.c \
common/sec2/sec2_allocator.c \
common/sec2/sec2_ipc.c \
common/sec2/sec2_msg.c \
common/sec2/sec2_queue.c \
common/sec2/sec2_seq.c \
common/ptimer/ptimer.c \

5
drivers/gpu/nvgpu/common/sec2/sec2.c
View File

@@ -27,8 +27,9 @@
#include <nvgpu/sec2.h>
#include <nvgpu/sec2/queue.h>
#include <nvgpu/sec2/seq.h>
#include <nvgpu/sec2if/sec2_if_sec2.h>
#include <nvgpu/sec2if/sec2_if_cmn.h>
#include <nvgpu/sec2/allocator.h>
#include <nvgpu/sec2/msg.h>
static void nvgpu_remove_sec2_support(struct nvgpu_sec2 *sec2)
{
@@ -96,6 +97,8 @@ int nvgpu_sec2_destroy(struct gk20a *g)
nvgpu_log_fn(g, " ");
nvgpu_sec2_dmem_allocator_destroy(&sec2->dmem);
nvgpu_mutex_acquire(&sec2->isr_mutex);
sec2->isr_enabled = false;
nvgpu_mutex_release(&sec2->isr_mutex);

51
drivers/gpu/nvgpu/common/sec2/sec2_allocator.c Normal file
View File

@@ -0,0 +1,51 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/sec2/allocator.h>
#include <nvgpu/allocator.h>
#include <nvgpu/sec2/msg.h>
void nvgpu_sec2_dmem_allocator_init(struct gk20a *g,
struct nvgpu_allocator *dmem,
struct sec2_init_msg_sec2_init *sec2_init)
{
if (!nvgpu_alloc_initialized(dmem)) {
/* Align start and end addresses */
u32 start = ALIGN(sec2_init->nv_managed_area_offset,
PMU_DMEM_ALLOC_ALIGNMENT);
u32 end = (sec2_init->nv_managed_area_offset +
sec2_init->nv_managed_area_size) &
~(PMU_DMEM_ALLOC_ALIGNMENT - 1U);
u32 size = end - start;
nvgpu_bitmap_allocator_init(g, dmem, "sec2_dmem",
start, size, PMU_DMEM_ALLOC_ALIGNMENT, 0U);
}
}
void nvgpu_sec2_dmem_allocator_destroy(struct nvgpu_allocator *dmem)
{
if (nvgpu_alloc_initialized(dmem)) {
nvgpu_alloc_destroy(dmem);
}
}

184
drivers/gpu/nvgpu/common/sec2/sec2_ipc.c
View File

@@ -29,7 +29,6 @@
#include <nvgpu/sec2.h>
#include <nvgpu/engine_queue.h>
#include <nvgpu/sec2/queue.h>
#include <nvgpu/sec2if/sec2_if_sec2.h>
#include <nvgpu/sec2if/sec2_if_cmn.h>
/* command post operation functions */
@@ -145,189 +144,6 @@ exit:
return err;
}
/* Message/Event request handlers */
static int sec2_response_handle(struct nvgpu_sec2 *sec2,
struct nv_flcn_msg_sec2 *msg)
{
struct gk20a *g = sec2->g;
return nvgpu_sec2_seq_response_handle(g, &sec2->sequences,
msg, msg->hdr.seq_id);
}
static int sec2_handle_event(struct nvgpu_sec2 *sec2,
struct nv_flcn_msg_sec2 *msg)
{
int err = 0;
switch (msg->hdr.unit_id) {
default:
break;
}
return err;
}
static bool sec2_read_message(struct nvgpu_sec2 *sec2,
u32 queue_id, struct nv_flcn_msg_sec2 *msg, int *status)
{
struct gk20a *g = sec2->g;
u32 read_size;
int err;
*status = 0;
if (nvgpu_sec2_queue_is_empty(sec2->queues, queue_id)) {
return false;
}
if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
&sec2->flcn, &msg->hdr,
PMU_MSG_HDR_SIZE, status)) {
nvgpu_err(g, "fail to read msg from queue %d", queue_id);
goto clean_up;
}
if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) {
err = nvgpu_sec2_queue_rewind(&sec2->flcn,
sec2->queues, queue_id);
if (err != 0) {
nvgpu_err(g, "fail to rewind queue %d", queue_id);
*status = err;
goto clean_up;
}
/* read again after rewind */
if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
&sec2->flcn, &msg->hdr,
PMU_MSG_HDR_SIZE, status)) {
nvgpu_err(g, "fail to read msg from queue %d",
queue_id);
goto clean_up;
}
}
if (!NV_SEC2_UNITID_IS_VALID(msg->hdr.unit_id)) {
nvgpu_err(g, "read invalid unit_id %d from queue %d",
msg->hdr.unit_id, queue_id);
*status = -EINVAL;
goto clean_up;
}
if (msg->hdr.size > PMU_MSG_HDR_SIZE) {
read_size = msg->hdr.size - PMU_MSG_HDR_SIZE;
if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
&sec2->flcn, &msg->msg,
read_size, status)) {
nvgpu_err(g, "fail to read msg from queue %d",
queue_id);
goto clean_up;
}
}
return true;
clean_up:
return false;
}
static int sec2_process_init_msg(struct nvgpu_sec2 *sec2,
struct nv_flcn_msg_sec2 *msg)
{
struct gk20a *g = sec2->g;
struct sec2_init_msg_sec2_init *sec2_init;
u32 tail = 0;
int err = 0;
g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET);
err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail,
(u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0U);
if (err != 0) {
goto exit;
}
if (msg->hdr.unit_id != NV_SEC2_UNIT_INIT) {
nvgpu_err(g, "expecting init msg");
err = -EINVAL;
goto exit;
}
err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail + PMU_MSG_HDR_SIZE,
(u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0U);
if (err != 0) {
goto exit;
}
if (msg->msg.init.msg_type != PMU_INIT_MSG_TYPE_PMU_INIT) {
nvgpu_err(g, "expecting init msg");
err = -EINVAL;
goto exit;
}
tail += ALIGN(msg->hdr.size, PMU_DMEM_ALIGNMENT);
g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_SET);
sec2_init = &msg->msg.init.sec2_init;
err = nvgpu_sec2_queues_init(g, sec2->queues, sec2_init);
if (err != 0) {
return err;
}
if (!nvgpu_alloc_initialized(&sec2->dmem)) {
/* Align start and end addresses */
u32 start = ALIGN(sec2_init->nv_managed_area_offset,
PMU_DMEM_ALLOC_ALIGNMENT);
u32 end = (sec2_init->nv_managed_area_offset +
sec2_init->nv_managed_area_size) &
~(PMU_DMEM_ALLOC_ALIGNMENT - 1U);
u32 size = end - start;
nvgpu_bitmap_allocator_init(g, &sec2->dmem, "sec2_dmem",
start, size, PMU_DMEM_ALLOC_ALIGNMENT, 0U);
}
sec2->sec2_ready = true;
exit:
return err;
}
int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2)
{
struct gk20a *g = sec2->g;
struct nv_flcn_msg_sec2 msg;
int status = 0;
if (unlikely(!sec2->sec2_ready)) {
status = sec2_process_init_msg(sec2, &msg);
goto exit;
}
while (sec2_read_message(sec2,
SEC2_NV_MSGQ_LOG_ID, &msg, &status)) {
nvgpu_sec2_dbg(g, "read msg hdr: ");
nvgpu_sec2_dbg(g, "unit_id = 0x%08x, size = 0x%08x",
msg.hdr.unit_id, msg.hdr.size);
nvgpu_sec2_dbg(g, "ctrl_flags = 0x%08x, seq_id = 0x%08x",
msg.hdr.ctrl_flags, msg.hdr.seq_id);
msg.hdr.ctrl_flags &= ~PMU_CMD_FLAGS_PMU_MASK;
if (msg.hdr.ctrl_flags == PMU_CMD_FLAGS_EVENT) {
sec2_handle_event(sec2, &msg);
} else {
sec2_response_handle(sec2, &msg);
}
}
exit:
return status;
}
int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
void *var, u8 val)
{

201
drivers/gpu/nvgpu/common/sec2/sec2_msg.c Normal file
View File

@@ -0,0 +1,201 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/sec2if/sec2_if_cmn.h>
#include <nvgpu/sec2/allocator.h>
#include <nvgpu/engine_queue.h>
#include <nvgpu/sec2/queue.h>
#include <nvgpu/flcnif_cmn.h>
#include <nvgpu/sec2/msg.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/sec2.h>
/* Message/Event request handlers */
static int sec2_response_handle(struct nvgpu_sec2 *sec2,
struct nv_flcn_msg_sec2 *msg)
{
struct gk20a *g = sec2->g;
return nvgpu_sec2_seq_response_handle(g, &sec2->sequences,
msg, msg->hdr.seq_id);
}
static int sec2_handle_event(struct nvgpu_sec2 *sec2,
struct nv_flcn_msg_sec2 *msg)
{
int err = 0;
switch (msg->hdr.unit_id) {
default:
break;
}
return err;
}
static bool sec2_read_message(struct nvgpu_sec2 *sec2,
u32 queue_id, struct nv_flcn_msg_sec2 *msg, int *status)
{
struct gk20a *g = sec2->g;
u32 read_size;
int err;
*status = 0U;
if (nvgpu_sec2_queue_is_empty(sec2->queues, queue_id)) {
return false;
}
if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
&sec2->flcn, &msg->hdr,
PMU_MSG_HDR_SIZE, status)) {
nvgpu_err(g, "fail to read msg from queue %d", queue_id);
goto clean_up;
}
if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) {
err = nvgpu_sec2_queue_rewind(&sec2->flcn,
sec2->queues, queue_id);
if (err != 0) {
nvgpu_err(g, "fail to rewind queue %d", queue_id);
*status = err;
goto clean_up;
}
/* read again after rewind */
if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
&sec2->flcn, &msg->hdr,
PMU_MSG_HDR_SIZE, status)) {
nvgpu_err(g, "fail to read msg from queue %d",
queue_id);
goto clean_up;
}
}
if (!NV_SEC2_UNITID_IS_VALID(msg->hdr.unit_id)) {
nvgpu_err(g, "read invalid unit_id %d from queue %d",
msg->hdr.unit_id, queue_id);
*status = -EINVAL;
goto clean_up;
}
if (msg->hdr.size > PMU_MSG_HDR_SIZE) {
read_size = msg->hdr.size - PMU_MSG_HDR_SIZE;
if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
&sec2->flcn, &msg->msg,
read_size, status)) {
nvgpu_err(g, "fail to read msg from queue %d",
queue_id);
goto clean_up;
}
}
return true;
clean_up:
return false;
}
static int sec2_process_init_msg(struct nvgpu_sec2 *sec2,
struct nv_flcn_msg_sec2 *msg)
{
struct gk20a *g = sec2->g;
struct sec2_init_msg_sec2_init *sec2_init;
u32 tail = 0;
int err = 0;
g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET);
err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail,
(u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0U);
if (err != 0) {
goto exit;
}
if (msg->hdr.unit_id != NV_SEC2_UNIT_INIT) {
nvgpu_err(g, "expecting init msg");
err = -EINVAL;
goto exit;
}
err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail + PMU_MSG_HDR_SIZE,
(u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0U);
if (err != 0) {
goto exit;
}
if (msg->msg.init.msg_type != NV_SEC2_INIT_MSG_ID_SEC2_INIT) {
nvgpu_err(g, "expecting init msg");
err = -EINVAL;
goto exit;
}
tail += ALIGN(msg->hdr.size, PMU_DMEM_ALIGNMENT);
g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_SET);
sec2_init = &msg->msg.init.sec2_init;
err = nvgpu_sec2_queues_init(g, sec2->queues, sec2_init);
if (err != 0) {
return err;
}
nvgpu_sec2_dmem_allocator_init(g, &sec2->dmem, sec2_init);
sec2->sec2_ready = true;
exit:
return err;
}
int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2)
{
struct gk20a *g = sec2->g;
struct nv_flcn_msg_sec2 msg;
int status = 0;
if (unlikely(!sec2->sec2_ready)) {
status = sec2_process_init_msg(sec2, &msg);
goto exit;
}
while (sec2_read_message(sec2,
SEC2_NV_MSGQ_LOG_ID, &msg, &status)) {
nvgpu_sec2_dbg(g, "read msg hdr: ");
nvgpu_sec2_dbg(g, "unit_id = 0x%08x, size = 0x%08x",
msg.hdr.unit_id, msg.hdr.size);
nvgpu_sec2_dbg(g, "ctrl_flags = 0x%08x, seq_id = 0x%08x",
msg.hdr.ctrl_flags, msg.hdr.seq_id);
msg.hdr.ctrl_flags &= ~PMU_CMD_FLAGS_PMU_MASK;
if (msg.hdr.ctrl_flags == PMU_CMD_FLAGS_EVENT) {
sec2_handle_event(sec2, &msg);
} else {
sec2_response_handle(sec2, &msg);
}
}
exit:
return status;
}

3
drivers/gpu/nvgpu/common/sec2/sec2_queue.c
View File

@@ -20,11 +20,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/sec2if/sec2_if_sec2.h>
#include <nvgpu/engine_mem_queue.h>
#include <nvgpu/sec2/queue_cmn.h>
#include <nvgpu/engine_queue.h>
#include <nvgpu/sec2/queue.h>
#include <nvgpu/sec2/msg.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/log.h>

1
drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
View File

@@ -24,6 +24,7 @@
#define NVGPU_FLCNIF_CMN_H
#include <nvgpu/types.h>
#include <nvgpu/bitops.h>
#define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0U

3
drivers/gpu/nvgpu/include/nvgpu/sec2.h
View File

@@ -32,9 +32,9 @@
#include <nvgpu/falcon.h>
#include <nvgpu/engine_mem_queue.h>
#include <nvgpu/sec2/seq.h>
#include <nvgpu/sec2/queue_cmn.h>
#include <nvgpu/sec2if/sec2_cmd_if.h>
#include <nvgpu/sec2if/sec2_if_sec2.h>
#define nvgpu_sec2_dbg(g, fmt, args...) \
nvgpu_log(g, gpu_dbg_pmu, fmt, ##args)
@@ -72,7 +72,6 @@ struct nvgpu_sec2 {
int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd,
u32 queue_id, sec2_callback callback,
void *cb_param, u32 timeout);
int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2);
int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
void *var, u8 val);

35
drivers/gpu/nvgpu/include/nvgpu/sec2/allocator.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SEC2_ALLOCATOR_H
#define NVGPU_SEC2_ALLOCATOR_H
struct gk20a;
struct nvgpu_allocator;
struct sec2_init_msg_sec2_init;
void nvgpu_sec2_dmem_allocator_init(struct gk20a *g,
struct nvgpu_allocator *dmem,
struct sec2_init_msg_sec2_init *sec2_init);
void nvgpu_sec2_dmem_allocator_destroy(struct nvgpu_allocator *dmem);
#endif /* NVGPU_SEC2_ALLOCATOR_H */

30
drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h → drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h
View File

@@ -20,14 +20,18 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SEC2_IF_SEC2_H
#define NVGPU_SEC2_IF_SEC2_H
#ifndef NVGPU_SEC2_MSG_H
#define NVGPU_SEC2_MSG_H
#include <nvgpu/sec2if/sec2_if_acr.h>
#include <nvgpu/sec2/queue_cmn.h>
#include <nvgpu/flcnif_cmn.h>
#include <nvgpu/types.h>
struct nvgpu_sec2;
/*
* SEC2 Command/Message Interfaces - SEC2 Management
* SEC2 Message Interfaces - SEC2 Management
*/
/*
@@ -35,8 +39,7 @@
* messages.
* _SEC2_INIT - sec2_init_msg_sec2_init
*/
enum
{
enum {
NV_SEC2_INIT_MSG_ID_SEC2_INIT = 0U,
};
@@ -46,8 +49,7 @@ struct sec2_init_msg_sec2_init {
u16 os_debug_entry_point;
struct
{
struct {
u32 queue_offset;
u16 queue_size;
u8 queue_phy_id;
@@ -63,4 +65,16 @@ union nv_flcn_msg_sec2_init {
struct sec2_init_msg_sec2_init sec2_init;
};
#endif /* NVGPU_SEC2_IF_SEC2_H */
struct nv_flcn_msg_sec2 {
struct pmu_hdr hdr;
union {
union nv_flcn_msg_sec2_init init;
union nv_sec2_acr_msg acr;
} msg;
};
int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2);
#endif /* NVGPU_SEC2_MSG_H */

12
drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -23,7 +23,6 @@
#ifndef NVGPU_SEC2_CMD_IF_H
#define NVGPU_SEC2_CMD_IF_H
#include <nvgpu/sec2if/sec2_if_sec2.h>
#include <nvgpu/sec2if/sec2_if_acr.h>
struct nv_flcn_cmd_sec2 {
@@ -33,15 +32,6 @@ struct nv_flcn_cmd_sec2 {
} cmd;
};
struct nv_flcn_msg_sec2 {
struct pmu_hdr hdr;
union {
union nv_flcn_msg_sec2_init init;
union nv_sec2_acr_msg acr;
} msg;
};
#define NV_SEC2_UNIT_REWIND NV_FLCN_UNIT_ID_REWIND
#define NV_SEC2_UNIT_INIT (0x01U)
#define NV_SEC2_UNIT_ACR (0x07U)

1
drivers/gpu/nvgpu/tu104/sec2_tu104.c
View File

@@ -29,6 +29,7 @@
#include <nvgpu/falcon.h>
#include <nvgpu/engine_mem_queue.h>
#include <nvgpu/sec2.h>
#include <nvgpu/sec2/msg.h>
#include <nvgpu/bug.h>
#include "sec2_tu104.h"