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gpu: nvgpu: prepare sec2 msg, allocator units
SEC2 message handling unit can't be part of command handling unit as it creates circular dependencies with the SEC2 tasks (ACR bootstrap) SEC2 allocator unit shall encompass DMEM allocator and other allocators used by SEC2. JIRA NVGPU-2075 Change-Id: Ic2b8204d8225f2056785f035cbecdb776a9ecfe9 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085749 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
committed by
mobile promotions
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parent
eef3ef7773
commit
e848e9dfb8
@@ -29,7 +29,6 @@
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#include <nvgpu/sec2.h>
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#include <nvgpu/engine_queue.h>
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#include <nvgpu/sec2/queue.h>
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#include <nvgpu/sec2if/sec2_if_sec2.h>
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#include <nvgpu/sec2if/sec2_if_cmn.h>
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/* command post operation functions */
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@@ -145,189 +144,6 @@ exit:
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return err;
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}
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/* Message/Event request handlers */
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static int sec2_response_handle(struct nvgpu_sec2 *sec2,
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struct nv_flcn_msg_sec2 *msg)
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{
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struct gk20a *g = sec2->g;
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return nvgpu_sec2_seq_response_handle(g, &sec2->sequences,
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msg, msg->hdr.seq_id);
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}
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static int sec2_handle_event(struct nvgpu_sec2 *sec2,
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struct nv_flcn_msg_sec2 *msg)
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{
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int err = 0;
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switch (msg->hdr.unit_id) {
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default:
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break;
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}
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return err;
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}
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static bool sec2_read_message(struct nvgpu_sec2 *sec2,
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u32 queue_id, struct nv_flcn_msg_sec2 *msg, int *status)
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{
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struct gk20a *g = sec2->g;
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u32 read_size;
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int err;
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*status = 0;
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if (nvgpu_sec2_queue_is_empty(sec2->queues, queue_id)) {
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return false;
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}
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if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
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&sec2->flcn, &msg->hdr,
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PMU_MSG_HDR_SIZE, status)) {
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nvgpu_err(g, "fail to read msg from queue %d", queue_id);
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goto clean_up;
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}
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if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) {
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err = nvgpu_sec2_queue_rewind(&sec2->flcn,
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sec2->queues, queue_id);
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if (err != 0) {
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nvgpu_err(g, "fail to rewind queue %d", queue_id);
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*status = err;
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goto clean_up;
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}
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/* read again after rewind */
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if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
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&sec2->flcn, &msg->hdr,
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PMU_MSG_HDR_SIZE, status)) {
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nvgpu_err(g, "fail to read msg from queue %d",
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queue_id);
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goto clean_up;
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}
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}
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if (!NV_SEC2_UNITID_IS_VALID(msg->hdr.unit_id)) {
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nvgpu_err(g, "read invalid unit_id %d from queue %d",
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msg->hdr.unit_id, queue_id);
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*status = -EINVAL;
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goto clean_up;
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}
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if (msg->hdr.size > PMU_MSG_HDR_SIZE) {
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read_size = msg->hdr.size - PMU_MSG_HDR_SIZE;
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if (!nvgpu_sec2_queue_read(g, sec2->queues, queue_id,
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&sec2->flcn, &msg->msg,
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read_size, status)) {
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nvgpu_err(g, "fail to read msg from queue %d",
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queue_id);
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goto clean_up;
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}
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}
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return true;
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clean_up:
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return false;
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}
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static int sec2_process_init_msg(struct nvgpu_sec2 *sec2,
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struct nv_flcn_msg_sec2 *msg)
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{
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struct gk20a *g = sec2->g;
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struct sec2_init_msg_sec2_init *sec2_init;
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u32 tail = 0;
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int err = 0;
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g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET);
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err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail,
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(u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0U);
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if (err != 0) {
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goto exit;
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}
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if (msg->hdr.unit_id != NV_SEC2_UNIT_INIT) {
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nvgpu_err(g, "expecting init msg");
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err = -EINVAL;
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goto exit;
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}
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err = nvgpu_falcon_copy_from_emem(&sec2->flcn, tail + PMU_MSG_HDR_SIZE,
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(u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0U);
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if (err != 0) {
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goto exit;
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}
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if (msg->msg.init.msg_type != PMU_INIT_MSG_TYPE_PMU_INIT) {
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nvgpu_err(g, "expecting init msg");
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err = -EINVAL;
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goto exit;
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}
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tail += ALIGN(msg->hdr.size, PMU_DMEM_ALIGNMENT);
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g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_SET);
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sec2_init = &msg->msg.init.sec2_init;
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err = nvgpu_sec2_queues_init(g, sec2->queues, sec2_init);
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if (err != 0) {
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return err;
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}
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if (!nvgpu_alloc_initialized(&sec2->dmem)) {
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/* Align start and end addresses */
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u32 start = ALIGN(sec2_init->nv_managed_area_offset,
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PMU_DMEM_ALLOC_ALIGNMENT);
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u32 end = (sec2_init->nv_managed_area_offset +
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sec2_init->nv_managed_area_size) &
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~(PMU_DMEM_ALLOC_ALIGNMENT - 1U);
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u32 size = end - start;
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nvgpu_bitmap_allocator_init(g, &sec2->dmem, "sec2_dmem",
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start, size, PMU_DMEM_ALLOC_ALIGNMENT, 0U);
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}
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sec2->sec2_ready = true;
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exit:
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return err;
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}
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int nvgpu_sec2_process_message(struct nvgpu_sec2 *sec2)
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{
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struct gk20a *g = sec2->g;
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struct nv_flcn_msg_sec2 msg;
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int status = 0;
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if (unlikely(!sec2->sec2_ready)) {
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status = sec2_process_init_msg(sec2, &msg);
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goto exit;
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}
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while (sec2_read_message(sec2,
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SEC2_NV_MSGQ_LOG_ID, &msg, &status)) {
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nvgpu_sec2_dbg(g, "read msg hdr: ");
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nvgpu_sec2_dbg(g, "unit_id = 0x%08x, size = 0x%08x",
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msg.hdr.unit_id, msg.hdr.size);
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nvgpu_sec2_dbg(g, "ctrl_flags = 0x%08x, seq_id = 0x%08x",
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msg.hdr.ctrl_flags, msg.hdr.seq_id);
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msg.hdr.ctrl_flags &= ~PMU_CMD_FLAGS_PMU_MASK;
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if (msg.hdr.ctrl_flags == PMU_CMD_FLAGS_EVENT) {
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sec2_handle_event(sec2, &msg);
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} else {
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sec2_response_handle(sec2, &msg);
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}
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}
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exit:
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return status;
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}
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int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms,
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void *var, u8 val)
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{
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