gpu: nvgpu: add GSP and CTRL CG support

Add SLCG clock gating support for GSP and CTRL units
Bug 3452217

Change-Id: Ic014fc03c8f4ad951b1fba8ab7b3e1cd1a23a59c
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2678680
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Divya
2022-03-09 06:55:39 +00:00
committed by mobile promotions
parent 40231858a5
commit e9563e40d1
2 changed files with 78 additions and 2 deletions

View File

@@ -31,7 +31,6 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/fifo.h>
#include <nvgpu/runlist.h>
#include "hal/power_features/cg/gating_reglist.h"
#include "ga10b_gating_reglist.h"
@@ -168,6 +167,19 @@ static const struct gating_desc ga10b_slcg_hshub[] = {
{.addr = 0x00004bf4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
};
/* slcg Ctrl */
static const struct gating_desc ga10b_slcg_ctrl[] = {
{.addr = 0x00b66a00U, .prod = 0x00000000U, .disable = 0x00000006U},
};
/* slcg GSP */
static const struct gating_desc ga10b_slcg_gsp[] = {
{.addr = 0x00110134U, .prod = 0x00040140U, .disable = 0x0003fffeU},
{.addr = 0x00110674U, .prod = 0x00000000U, .disable = 0x0000000fU},
{.addr = 0x00110e28U, .prod = 0x00000000U, .disable = 0x00000001U},
{.addr = 0x0011083cU, .prod = 0x000000feU, .disable = 0x800000ffU},
};
/* slcg timer */
static const struct gating_desc ga10b_slcg_timer[] = {
{.addr = 0x00009600U, .prod = 0x00000000U, .disable = 0x00000002U},
@@ -881,6 +893,60 @@ const struct gating_desc *ga10b_slcg_hshub_get_gating_prod(void)
return ga10b_slcg_hshub;
}
void ga10b_slcg_ctrl_load_gating_prod(struct gk20a *g,
bool prod)
{
u32 i;
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_ctrl)
/ GATING_DESC_SIZE);
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
for (i = 0U; i < size; i++) {
u32 reg = ga10b_slcg_ctrl[i].addr;
u32 val = prod ? ga10b_slcg_ctrl[i].prod :
ga10b_slcg_ctrl[i].disable;
nvgpu_writel(g, reg, val);
}
}
}
u32 ga10b_slcg_ctrl_gating_prod_size(void)
{
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_ctrl));
}
const struct gating_desc *ga10b_slcg_ctrl_get_gating_prod(void)
{
return ga10b_slcg_ctrl;
}
void ga10b_slcg_gsp_load_gating_prod(struct gk20a *g,
bool prod)
{
u32 i;
u32 size = nvgpu_safe_cast_u64_to_u32(sizeof(ga10b_slcg_gsp)
/ GATING_DESC_SIZE);
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
for (i = 0U; i < size; i++) {
u32 reg = ga10b_slcg_gsp[i].addr;
u32 val = prod ? ga10b_slcg_gsp[i].prod :
ga10b_slcg_gsp[i].disable;
nvgpu_writel(g, reg, val);
}
}
}
u32 ga10b_slcg_gsp_gating_prod_size(void)
{
return nvgpu_safe_cast_u64_to_u32(ARRAY_SIZE(ga10b_slcg_gsp));
}
const struct gating_desc *ga10b_slcg_gsp_get_gating_prod(void)
{
return ga10b_slcg_gsp;
}
void ga10b_blcg_bus_load_gating_prod(struct gk20a *g,
bool prod)
{

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -130,6 +130,16 @@ void ga10b_slcg_hshub_load_gating_prod(struct gk20a *g,
u32 ga10b_slcg_hshub_gating_prod_size(void);
const struct gating_desc *ga10b_slcg_hshub_get_gating_prod(void);
void ga10b_slcg_ctrl_load_gating_prod(struct gk20a *g,
bool prod);
u32 ga10b_slcg_ctrl_gating_prod_size(void);
const struct gating_desc *ga10b_slcg_ctrl_get_gating_prod(void);
void ga10b_slcg_gsp_load_gating_prod(struct gk20a *g,
bool prod);
u32 ga10b_slcg_gsp_gating_prod_size(void);
const struct gating_desc *ga10b_slcg_gsp_get_gating_prod(void);
void ga10b_blcg_bus_load_gating_prod(struct gk20a *g,
bool prod);
u32 ga10b_blcg_bus_gating_prod_size(void);