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gpu: nvgpu: remove wait_fence_fd from incr_user

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The wait_fence_fd parameter in nvgpu_channel_sync_incr_user() has not
been used since commit 1a4647272f ("gpu: nvgpu: remove fence
dependency tracking") where it was used to save a dependency fd to
sema-based post fences. The commit probably should have removed this
param; it has no purpose in the current design.

Jira NVGPU-4548

Change-Id: Id7e68b24f8e9ba0e43ff01b7af946434580b166e
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2326604
(cherry picked from commit f8031142270fb87ac41597ae70a80505078ae6d5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328423
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Hölttä
2020-04-09 16:16:38 +03:00
committed by Alex Waterman
parent aa1322f975
commit e9747d5477
6 changed files with 12 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/fifo/submit.c
View File

@@ -151,9 +151,8 @@ static int nvgpu_submit_prepare_syncs(struct nvgpu_channel *c,
if (flag_fence_get) {
err = nvgpu_channel_sync_incr_user(c->sync,
wait_fence_fd, job->incr_cmd,
job->post_fence, need_wfi, need_sync_fence,
register_irq);
job->incr_cmd, job->post_fence, need_wfi,
need_sync_fence, register_irq);
} else {
err = nvgpu_channel_sync_incr(c->sync,
job->incr_cmd, job->post_fence, need_sync_fence,

11
drivers/gpu/nvgpu/common/sync/channel_sync.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A Channel Synchronization Abstraction
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -71,12 +71,11 @@ int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
}
int nvgpu_channel_sync_incr_user(struct nvgpu_channel_sync *s,
int wait_fence_fd, struct priv_cmd_entry *entry,
struct nvgpu_fence_type *fence, bool wfi, bool need_sync_fence,
bool register_irq)
struct priv_cmd_entry *entry, struct nvgpu_fence_type *fence, bool wfi,
bool need_sync_fence, bool register_irq)
{
return s->ops->incr_user(s, wait_fence_fd, entry, fence, wfi,
need_sync_fence, register_irq);
return s->ops->incr_user(s, entry, fence, wfi, need_sync_fence,
register_irq);
}
void nvgpu_channel_sync_set_min_eq_max(struct nvgpu_channel_sync *s)

4
drivers/gpu/nvgpu/common/sync/channel_sync_priv.h
View File

@@ -1,8 +1,7 @@
/*
*
* Nvgpu Channel Synchronization Abstraction
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -67,7 +66,6 @@ struct nvgpu_channel_sync_ops {
bool register_irq);
int (*incr_user)(struct nvgpu_channel_sync *s,
int wait_fence_fd,
struct priv_cmd_entry *entry,
struct nvgpu_fence_type *fence,
bool wfi,

3
drivers/gpu/nvgpu/common/sync/channel_sync_semaphore.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A Channel Synchronization Abstraction
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -243,7 +243,6 @@ static int channel_sync_semaphore_incr(
static int channel_sync_semaphore_incr_user(
struct nvgpu_channel_sync *s,
int wait_fence_fd,
struct priv_cmd_entry *entry,
struct nvgpu_fence_type *fence,
bool wfi,

1
drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c
View File

@@ -263,7 +263,6 @@ static int channel_sync_syncpt_incr(struct nvgpu_channel_sync *s,
}
static int channel_sync_syncpt_incr_user(struct nvgpu_channel_sync *s,
int wait_fence_fd,
struct priv_cmd_entry *entry,
struct nvgpu_fence_type *fence,
bool wfi,

8
drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
View File

@@ -1,8 +1,7 @@
/*
*
* Nvgpu Channel Synchronization Abstraction
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -65,9 +64,8 @@ int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
* - a nvgpu_fence_type that signals when the incr has happened.
*/
int nvgpu_channel_sync_incr_user(struct nvgpu_channel_sync *s,
int wait_fence_fd, struct priv_cmd_entry *entry,
struct nvgpu_fence_type *fence, bool wfi, bool need_sync_fence,
bool register_irq);
struct priv_cmd_entry *entry, struct nvgpu_fence_type *fence, bool wfi,
bool need_sync_fence, bool register_irq);
/*
* Reset the channel syncpoint/semaphore. Syncpoint increments generally
* wrap around the range of integer values. Current max value encompasses