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gpu: nvgpu: SWUD Lite updates

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Updated minor typo errors found during code inspection

JIRA NVGPU-4785
JIRA NVGPU-4789

Change-Id: I37384a852e9a2783e3033a6f12c21eafc00e5bcf
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300560
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Divya Singhatwaria
2020-02-20 17:40:15 +05:30
committed by Alex Waterman
parent 43324f7b1b
commit ed4eb79ac1
4 changed files with 12 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h
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@@ -36,7 +36,6 @@ void gv11b_setup_apertures(struct gk20a *g);
bool gv11b_pmu_is_engine_in_reset(struct gk20a *g);
void gv11b_pmu_engine_reset(struct gk20a *g, bool do_reset);
u32 gv11b_pmu_falcon_base_addr(void);
void gv11b_secured_pmu_start(struct gk20a *g);
bool gv11b_is_pmu_supported(struct gk20a *g);
int gv11b_pmu_correct_ecc(struct gk20a *g, u32 ecc_status, u32 ecc_addr);
void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
@@ -45,6 +44,7 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
u32 args_offset);
void gv11b_pmu_setup_elpg(struct gk20a *g);
void gv11b_secured_pmu_start(struct gk20a *g);
void gv11b_write_dmatrfbase(struct gk20a *g, u32 addr);
u32 gv11b_pmu_queue_head_r(u32 i);
u32 gv11b_pmu_queue_head__size_1_v(void);

2
drivers/gpu/nvgpu/include/nvgpu/acr.h
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@@ -173,7 +173,7 @@ struct nvgpu_acr;
* + Allocate memory for ACR unit private struct #nvgpu_acr, return -ENOMEM upon
* failure else continue to next step.
* + Based on detected chip, init calls chip specific s/w init. For gv11b,
* nvgpu_gv11b_acr_sw_init is called to set. Static properties like
* nvgpu_gv11b_acr_sw_init is called to set static properties like
* bootstrap_owner, supported LS Falcons & ops update.
* + Struct #nvgpu_acr member gets set as below for gv11b,
* + FALCON_ID_PMU for bootstrap_owner as ACR HS ucode runs on PMU engine

19
drivers/gpu/nvgpu/include/nvgpu/gops_pmu.h
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@@ -182,16 +182,6 @@ struct gops_pmu {
*/
void (*setup_apertures)(struct gk20a *g);
/**
* @brief Start PMU falcon CPU in secure mode.
*
* @param g [in] The GPU driver struct.
*
* Start PMU falcon CPU in secure mode by writing true to
* CPUCTL_ALIAS.
*/
void (*secured_pmu_start)(struct gk20a *g);
/**
* @brief Clears the PMU BAR0 error status.
*
@@ -349,6 +339,15 @@ struct gops_pmu {
void (*pmu_dump_elpg_stats)(struct nvgpu_pmu *pmu);
void (*pmu_dump_falcon_stats)(struct nvgpu_pmu *pmu);
void (*dump_secure_fuses)(struct gk20a *g);
/**
* @brief Start PMU falcon CPU in secure mode.
*
* @param g [in] The GPU driver struct.
*
* Start PMU falcon CPU in secure mode by writing true to
* CPUCTL_ALIAS.
*/
void (*secured_pmu_start)(struct gk20a *g);
/**
* @brief Setup DMA transfer base address.
*

2
drivers/gpu/nvgpu/include/nvgpu/pmu.h
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@@ -370,7 +370,7 @@ void nvgpu_pmu_enable_irq(struct gk20a *g, bool enable);
*
* @param g [in] The GPU driver struct.
*
* Dose the PMU Engine reset to bring into good known state. The reset sequence
* Does the PMU Engine reset to bring into good known state. The reset sequence
* also configures PMU Engine clock gating & interrupts if interrupt support is
* enabled.
*