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gpu: nvgpu: move chip specific mc to hal

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Move chip specific mc code from common/mc to hal/mc.
Replace gk20a_readl/writel with nvgpu_readl/writel
Replace 0xFFFFFFFFU with U32_MAX hash define
Change local variable names to fix checkpatch errors/warnings
Change BUG to WARN
Move defines to header files
Create new defines for hard coded delays

JIRA NVGPU-2041

Change-Id: I3594121a81da37ef58c47e87c45e96441e4cf8c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085268
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-29 13:37:13 -07:00
committed by mobile promotions
parent 191aeb5cf8
commit f07d933076
19 changed files with 196 additions and 194 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/mc/mc.c
View File

@@ -32,7 +32,7 @@ u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
{
u32 val = __nvgpu_readl(g, mc_boot_0_r());
if (val != 0xffffffffU) {
if (val != U32_MAX) {
if (arch != NULL) {
*arch = mc_boot_0_architecture_v(val) <<

369
drivers/gpu/nvgpu/common/mc/mc_gm20b.c
View File

@@ -1,369 +0,0 @@
/*
* GM20B Master Control
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/timers.h>
#include <nvgpu/atomic.h>
#include <nvgpu/unit.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/ltc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include <nvgpu/engines.h>
#include <nvgpu/power_features/pg.h>
#include "mc_gm20b.h"
#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
void gm20b_mc_isr_stall(struct gk20a *g)
{
u32 mc_intr_0;
u32 engine_id_idx;
u32 active_engine_id = 0;
enum nvgpu_fifo_engine engine_enum;
mc_intr_0 = g->ops.mc.intr_stall(g);
nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
active_engine_id = g->fifo.active_engines_list[engine_id_idx];
if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
/* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
nvgpu_pg_elpg_protected_call(g, gk20a_gr_isr(g));
}
/* CE Engine */
if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
(g->ops.ce2.isr_stall != NULL)) {
g->ops.ce2.isr_stall(g,
g->fifo.engine_info[active_engine_id].inst_id,
g->fifo.engine_info[active_engine_id].pri_base);
}
}
}
if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) {
g->ops.fifo.intr_0_isr(g);
}
if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) {
g->ops.pmu.pmu_isr(g);
}
if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
g->ops.priv_ring.isr(g);
}
if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
g->ops.mc.ltc_isr(g);
}
if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
g->ops.bus.isr(g);
}
}
u32 gm20b_mc_isr_nonstall(struct gk20a *g)
{
u32 ops = 0;
u32 mc_intr_1;
u32 engine_id_idx;
u32 active_engine_id = 0;
enum nvgpu_fifo_engine engine_enum;
mc_intr_1 = g->ops.mc.intr_nonstall(g);
if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) {
ops |= g->ops.fifo.intr_1_isr(g);
}
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines;
engine_id_idx++) {
struct fifo_engine_info_gk20a *engine_info;
active_engine_id = g->fifo.active_engines_list[engine_id_idx];
engine_info = &g->fifo.engine_info[active_engine_id];
if ((mc_intr_1 & engine_info->intr_mask) != 0U) {
engine_enum = engine_info->engine_enum;
/* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
ops |= gk20a_gr_nonstall_isr(g);
}
/* CE Engine */
if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
(g->ops.ce2.isr_nonstall != NULL)) {
ops |= g->ops.ce2.isr_nonstall(g,
engine_info->inst_id,
engine_info->pri_base);
}
}
}
return ops;
}
void gm20b_mc_intr_mask(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_0_r(),
mc_intr_en_0_inta_disabled_f());
nvgpu_writel(g, mc_intr_en_1_r(),
mc_intr_en_1_inta_disabled_f());
}
void gm20b_mc_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_mask_1_r(),
mc_intr_pfifo_pending_f()
| eng_intr_mask);
gk20a_writel(g, mc_intr_en_1_r(),
mc_intr_en_1_inta_hardware_f());
gk20a_writel(g, mc_intr_mask_0_r(),
mc_intr_pfifo_pending_f()
| mc_intr_priv_ring_pending_f()
| mc_intr_ltc_pending_f()
| mc_intr_pbus_pending_f()
| eng_intr_mask);
gk20a_writel(g, mc_intr_en_0_r(),
mc_intr_en_0_inta_hardware_f());
}
void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask)
{
u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() :
mc_intr_mask_1_r());
if (enable) {
gk20a_writel(g, mask_reg,
gk20a_readl(g, mask_reg) |
mask);
} else {
gk20a_writel(g, mask_reg,
gk20a_readl(g, mask_reg) &
~mask);
}
}
void gm20b_mc_intr_stall_pause(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_0_r(),
mc_intr_en_0_inta_disabled_f());
/* flush previous write */
(void) gk20a_readl(g, mc_intr_en_0_r());
}
void gm20b_mc_intr_stall_resume(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_0_r(),
mc_intr_en_0_inta_hardware_f());
/* flush previous write */
(void) gk20a_readl(g, mc_intr_en_0_r());
}
void gm20b_mc_intr_nonstall_pause(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_1_r(),
mc_intr_en_0_inta_disabled_f());
/* flush previous write */
(void) gk20a_readl(g, mc_intr_en_1_r());
}
void gm20b_mc_intr_nonstall_resume(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_1_r(),
mc_intr_en_0_inta_hardware_f());
/* flush previous write */
(void) gk20a_readl(g, mc_intr_en_1_r());
}
u32 gm20b_mc_intr_stall(struct gk20a *g)
{
return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
}
u32 gm20b_mc_intr_nonstall(struct gk20a *g)
{
return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
}
void gm20b_mc_disable(struct gk20a *g, u32 units)
{
u32 pmc;
nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units);
nvgpu_spinlock_acquire(&g->mc_enable_lock);
pmc = gk20a_readl(g, mc_enable_r());
pmc &= ~units;
gk20a_writel(g, mc_enable_r(), pmc);
nvgpu_spinlock_release(&g->mc_enable_lock);
}
void gm20b_mc_enable(struct gk20a *g, u32 units)
{
u32 pmc;
nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units);
nvgpu_spinlock_acquire(&g->mc_enable_lock);
pmc = gk20a_readl(g, mc_enable_r());
pmc |= units;
gk20a_writel(g, mc_enable_r(), pmc);
pmc = gk20a_readl(g, mc_enable_r());
nvgpu_spinlock_release(&g->mc_enable_lock);
nvgpu_udelay(20);
}
void gm20b_mc_reset(struct gk20a *g, u32 units)
{
g->ops.mc.disable(g, units);
if ((units & nvgpu_engine_get_all_ce_reset_mask(g)) != 0U) {
nvgpu_udelay(500);
} else {
nvgpu_udelay(20);
}
g->ops.mc.enable(g, units);
}
bool gm20b_mc_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1)
{
u32 mask = 0U;
bool is_pending;
switch (unit) {
case NVGPU_UNIT_FIFO:
mask = mc_intr_pfifo_pending_f();
break;
default:
break;
}
if (mask == 0U) {
nvgpu_err(g, "unknown unit %d", unit);
is_pending = false;
} else {
is_pending = ((mc_intr_1 & mask) != 0U) ? true : false;
}
return is_pending;
}
void gm20b_mc_log_pending_intrs(struct gk20a *g)
{
u32 mc_intr_0;
u32 mc_intr_1;
mc_intr_0 = g->ops.mc.intr_stall(g);
if (mc_intr_0 != 0U) {
if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
/* clear priv ring interrupts */
g->ops.priv_ring.isr(g);
}
mc_intr_0 = g->ops.mc.intr_stall(g);
if (mc_intr_0 != 0U) {
nvgpu_info(g, "Pending stall intr0=0x%08x", mc_intr_0);
}
}
mc_intr_1 = g->ops.mc.intr_nonstall(g);
if (mc_intr_1 != 0U) {
nvgpu_info(g, "Pending nonstall intr1=0x%08x", mc_intr_1);
}
}
u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = 0;
switch(unit) {
case NVGPU_UNIT_FIFO:
mask = mc_enable_pfifo_enabled_f();
break;
case NVGPU_UNIT_PERFMON:
mask = mc_enable_perfmon_enabled_f();
break;
case NVGPU_UNIT_GRAPH:
mask = mc_enable_pgraph_enabled_f();
break;
case NVGPU_UNIT_BLG:
mask = mc_enable_blg_enabled_f();
break;
case NVGPU_UNIT_PWR:
mask = mc_enable_pwr_enabled_f();
break;
default:
nvgpu_err(g, "unknown reset unit %d", unit);
BUG();
break;
}
return mask;
}
bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = g->ops.mc.reset_mask(g, unit);
return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
}
void gm20b_mc_fb_reset(struct gk20a *g)
{
u32 val;
nvgpu_log_info(g, "reset gk20a fb");
val = gk20a_readl(g, mc_elpg_enable_r());
val |= mc_elpg_enable_xbar_enabled_f()
| mc_elpg_enable_pfb_enabled_f()
| mc_elpg_enable_hub_enabled_f();
gk20a_writel(g, mc_elpg_enable_r(), val);
}
void gm20b_mc_ltc_isr(struct gk20a *g)
{
u32 mc_intr;
u32 ltc;
mc_intr = gk20a_readl(g, mc_intr_ltc_r());
nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr);
for (ltc = 0; ltc < nvgpu_ltc_get_ltc_count(g); ltc++) {
if ((mc_intr & BIT32(ltc)) == 0U) {
continue;
}
g->ops.ltc.intr.isr(g, ltc);
}
}

55
drivers/gpu/nvgpu/common/mc/mc_gm20b.h
View File

@@ -1,55 +0,0 @@
/*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_MC_GM20B_H
#define NVGPU_MC_GM20B_H
#include <nvgpu/types.h>
struct gk20a;
enum nvgpu_unit;
void gm20b_mc_intr_mask(struct gk20a *g);
void gm20b_mc_intr_enable(struct gk20a *g);
void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask);
void gm20b_mc_isr_stall(struct gk20a *g);
u32 gm20b_mc_intr_stall(struct gk20a *g);
void gm20b_mc_intr_stall_pause(struct gk20a *g);
void gm20b_mc_intr_stall_resume(struct gk20a *g);
u32 gm20b_mc_intr_nonstall(struct gk20a *g);
u32 gm20b_mc_isr_nonstall(struct gk20a *g);
void gm20b_mc_intr_nonstall_pause(struct gk20a *g);
void gm20b_mc_intr_nonstall_resume(struct gk20a *g);
void gm20b_mc_enable(struct gk20a *g, u32 units);
void gm20b_mc_disable(struct gk20a *g, u32 units);
void gm20b_mc_reset(struct gk20a *g, u32 units);
bool gm20b_mc_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1);
void gm20b_mc_log_pending_intrs(struct gk20a *g);
void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops);
u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
void gm20b_mc_fb_reset(struct gk20a *g);
void gm20b_mc_ltc_isr(struct gk20a *g);
#endif /* NVGPU_MC_GM20B_H */

243
drivers/gpu/nvgpu/common/mc/mc_gp10b.c
View File

@@ -1,243 +0,0 @@
/*
* GP10B master
*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/ltc.h>
#include <nvgpu/engines.h>
#include <nvgpu/power_features/pg.h>
#include "mc_gp10b.h"
#include <nvgpu/atomic.h>
#include <nvgpu/unit.h>
#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
#define MAX_MC_INTR_REGS 2U
void mc_gp10b_intr_mask(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
}
void mc_gp10b_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
mc_intr_ltc_pending_f() |
mc_intr_replayable_fault_pending_f() |
eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f() |
eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask)
{
u32 intr_index = 0;
u32 reg = 0;
intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING :
NVGPU_MC_INTR_NONSTALLING);
if (enable) {
reg = mc_intr_en_set_r(intr_index);
g->mc_intr_mask_restore[intr_index] |= mask;
} else {
reg = mc_intr_en_clear_r(intr_index);
g->mc_intr_mask_restore[intr_index] &= ~mask;
}
gk20a_writel(g, reg, mask);
}
void mc_gp10b_isr_stall(struct gk20a *g)
{
u32 mc_intr_0;
u32 engine_id_idx;
u32 active_engine_id = 0;
enum nvgpu_fifo_engine engine_enum;
mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0);
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
active_engine_id = g->fifo.active_engines_list[engine_id_idx];
if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
/* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
nvgpu_pg_elpg_protected_call(g, gk20a_gr_isr(g));
}
/* CE Engine */
if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
(g->ops.ce2.isr_stall != NULL)) {
g->ops.ce2.isr_stall(g,
g->fifo.engine_info[active_engine_id].inst_id,
g->fifo.engine_info[active_engine_id].pri_base);
}
}
}
if ((g->ops.mc.is_intr_hub_pending != NULL) &&
g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) {
g->ops.fb.hub_isr(g);
}
if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) {
g->ops.fifo.intr_0_isr(g);
}
if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) {
g->ops.pmu.pmu_isr(g);
}
if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
g->ops.priv_ring.isr(g);
}
if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
g->ops.mc.ltc_isr(g);
}
if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
g->ops.bus.isr(g);
}
if ((g->ops.mc.is_intr_nvlink_pending != NULL) &&
g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) {
g->ops.nvlink.intr.isr(g);
}
if ((mc_intr_0 & mc_intr_pfb_pending_f()) != 0U &&
(g->ops.mc.fbpa_isr != NULL)) {
g->ops.mc.fbpa_isr(g);
}
nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0);
}
u32 mc_gp10b_intr_stall(struct gk20a *g)
{
return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
}
void mc_gp10b_intr_stall_pause(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffffU);
}
void mc_gp10b_intr_stall_resume(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
}
u32 mc_gp10b_intr_nonstall(struct gk20a *g)
{
return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
}
void mc_gp10b_intr_nonstall_pause(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
}
void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
bool mc_gp10b_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1)
{
u32 mask = 0;
bool is_pending;
switch (unit) {
case NVGPU_UNIT_FIFO:
mask = mc_intr_pfifo_pending_f();
break;
default:
break;
}
if (mask == 0U) {
nvgpu_err(g, "unknown unit %d", unit);
is_pending = false;
} else {
is_pending = ((mc_intr_1 & mask) != 0U) ? true : false;
}
return is_pending;
}
void mc_gp10b_log_pending_intrs(struct gk20a *g)
{
u32 i, intr;
for (i = 0; i < MAX_MC_INTR_REGS; i++) {
intr = nvgpu_readl(g, mc_intr_r(i));
if (intr == 0U) {
continue;
}
nvgpu_info(g, "Pending intr%d=0x%08x", i, intr);
}
}
void mc_gp10b_ltc_isr(struct gk20a *g)
{
u32 mc_intr;
u32 ltc;
mc_intr = gk20a_readl(g, mc_intr_ltc_r());
nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr);
for (ltc = 0; ltc < nvgpu_ltc_get_ltc_count(g); ltc++) {
if ((mc_intr & BIT32(ltc)) == 0U) {
continue;
}
g->ops.ltc.intr.isr(g, ltc);
}
}

48
drivers/gpu/nvgpu/common/mc/mc_gp10b.h
View File

@@ -1,48 +0,0 @@
/*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef MC_GP10B_H
#define MC_GP10B_H
#include <nvgpu/types.h>
struct gk20a;
enum nvgpu_unit;
void mc_gp10b_intr_mask(struct gk20a *g);
void mc_gp10b_intr_enable(struct gk20a *g);
void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask);
void mc_gp10b_isr_stall(struct gk20a *g);
bool mc_gp10b_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1);
void mc_gp10b_log_pending_intrs(struct gk20a *g);
u32 mc_gp10b_intr_stall(struct gk20a *g);
void mc_gp10b_intr_stall_pause(struct gk20a *g);
void mc_gp10b_intr_stall_resume(struct gk20a *g);
u32 mc_gp10b_intr_nonstall(struct gk20a *g);
void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
void mc_gp10b_ltc_isr(struct gk20a *g);
#endif

125
drivers/gpu/nvgpu/common/mc/mc_gv100.c
View File

@@ -1,125 +0,0 @@
/*
* GV100 master
*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/unit.h>
#include <nvgpu/bug.h>
#include <nvgpu/engines.h>
#include "mc_gp10b.h"
#include "mc_gv100.h"
#include <nvgpu/hw/gv100/hw_mc_gv100.h>
void mc_gv100_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_hub_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
mc_intr_ltc_pending_f() |
mc_intr_nvlink_pending_f() |
eng_intr_mask;
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f()
| eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
{
return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false);
}
bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
u32 *eng_intr_pending)
{
u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
u32 stall_intr, eng_intr_mask;
eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id);
*eng_intr_pending = mc_intr_0 & eng_intr_mask;
stall_intr = mc_intr_pfifo_pending_f() |
mc_intr_hub_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
mc_intr_ltc_pending_f() |
mc_intr_nvlink_pending_f();
nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
"mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
mc_intr_0 & stall_intr, *eng_intr_pending);
return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
}
u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = 0;
switch(unit) {
case NVGPU_UNIT_FIFO:
mask = mc_enable_pfifo_enabled_f();
break;
case NVGPU_UNIT_PERFMON:
mask = mc_enable_perfmon_enabled_f();
break;
case NVGPU_UNIT_GRAPH:
mask = mc_enable_pgraph_enabled_f();
break;
case NVGPU_UNIT_BLG:
mask = mc_enable_blg_enabled_f();
break;
case NVGPU_UNIT_PWR:
mask = mc_enable_pwr_enabled_f();
break;
case NVGPU_UNIT_NVDEC:
mask = mc_enable_nvdec_enabled_f();
break;
default:
nvgpu_err(g, "unknown reset unit %d", unit);
BUG();
break;
}
return mask;
}

36
drivers/gpu/nvgpu/common/mc/mc_gv100.h
View File

@@ -1,36 +0,0 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef MC_GV100_H
#define MC_GV100_H
#include <nvgpu/types.h>
struct gk20a;
void mc_gv100_intr_enable(struct gk20a *g);
bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0);
bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
u32 *eng_intr_pending);
u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
#endif

90
drivers/gpu/nvgpu/common/mc/mc_gv11b.c
View File

@@ -1,90 +0,0 @@
/*
* GV11B master
*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>
#include "mc_gp10b.h"
#include "mc_gv11b.h"
#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
void mc_gv11b_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_hub_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
mc_intr_ltc_pending_f() |
eng_intr_mask;
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f()
| eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
{
return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false);
}
bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
u32 *eng_intr_pending)
{
u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
u32 stall_intr, eng_intr_mask;
eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id);
*eng_intr_pending = mc_intr_0 & eng_intr_mask;
stall_intr = mc_intr_pfifo_pending_f() |
mc_intr_hub_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
mc_intr_ltc_pending_f();
nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
"mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
mc_intr_0 & stall_intr, *eng_intr_pending);
return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
}

34
drivers/gpu/nvgpu/common/mc/mc_gv11b.h
View File

@@ -1,34 +0,0 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef MC_GV11B_H
#define MC_GV11B_H
#include <nvgpu/types.h>
struct gk20a;
void mc_gv11b_intr_enable(struct gk20a *g);
bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
u32 *eng_intr_pending);
#endif

425
drivers/gpu/nvgpu/common/mc/mc_tu104.c
View File

@@ -1,425 +0,0 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/mc.h>
#include <nvgpu/ltc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>
#include "common/mc/mc_gp10b.h"
#include "mc_tu104.h"
#include "tu104/func_tu104.h"
#include "nvgpu/hw/tu104/hw_mc_tu104.h"
#include "nvgpu/hw/tu104/hw_func_tu104.h"
#include "nvgpu/hw/tu104/hw_ctrl_tu104.h"
/* helper to set leaf_reg_bit in LEAF_EN_SET(leaf_reg_index) register */
void intr_tu104_leaf_en_set(struct gk20a *g, u32 leaf_reg_index,
u32 leaf_reg_bit)
{
u32 val;
val = nvgpu_func_readl(g,
func_priv_cpu_intr_leaf_en_set_r(leaf_reg_index));
val |= BIT(leaf_reg_bit);
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_en_set_r(leaf_reg_index),
val);
}
/* helper to set leaf_reg_bit in LEAF_EN_CLEAR(leaf_reg_index) register */
void intr_tu104_leaf_en_clear(struct gk20a *g, u32 leaf_reg_index,
u32 leaf_reg_bit)
{
u32 val;
val = nvgpu_func_readl(g,
func_priv_cpu_intr_leaf_en_clear_r(leaf_reg_index));
val |= BIT(leaf_reg_bit);
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_en_clear_r(leaf_reg_index),
val);
}
/* helper to set leaf_reg_bit in LEAF(leaf_reg_index) register */
static void intr_tu104_leaf_clear(struct gk20a *g, u32 leaf_reg_index,
u32 leaf_reg_bit)
{
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_r(leaf_reg_index),
BIT(leaf_reg_bit));
}
/* helper to set top_reg_bit in TOP_EN_SET(top_reg_index) register */
void intr_tu104_top_en_set(struct gk20a *g, u32 top_reg_index,
u32 top_reg_bit)
{
u32 val;
val = nvgpu_func_readl(g,
func_priv_cpu_intr_top_en_set_r(top_reg_index));
val |= BIT(top_reg_bit);
nvgpu_func_writel(g,
func_priv_cpu_intr_top_en_set_r(top_reg_index),
val);
}
/* helper to enable interrupt vector in both LEAF and TOP registers */
void intr_tu104_vector_en_set(struct gk20a *g, u32 intr_vector)
{
intr_tu104_leaf_en_set(g,
NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(intr_vector),
NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(intr_vector));
intr_tu104_top_en_set(g,
NV_CPU_INTR_SUBTREE_TO_TOP_IDX(
NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(intr_vector)),
(NV_CPU_INTR_SUBTREE_TO_TOP_BIT(
NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(intr_vector))));
}
/* helper to disable interrupt vector in LEAF register */
void intr_tu104_vector_en_clear(struct gk20a *g, u32 intr_vector)
{
intr_tu104_leaf_en_clear(g,
NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(intr_vector),
NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(intr_vector));
}
/* helper to clear an interrupt vector in LEAF register */
void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector)
{
intr_tu104_leaf_clear(g,
NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(intr_vector),
NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(intr_vector));
}
/* helper to check if interrupt is pending for interrupt vector */
bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector)
{
u32 leaf_val;
leaf_val = nvgpu_func_readl(g,
func_priv_cpu_intr_leaf_r(
NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(intr_vector)));
return leaf_val &
BIT32(NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(intr_vector));
}
static void intr_tu104_stall_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
mc_intr_ltc_pending_f() |
mc_intr_nvlink_pending_f() |
mc_intr_pfb_pending_f() |
eng_intr_mask;
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
}
static void intr_tu104_nonstall_enable(struct gk20a *g)
{
u32 i;
u32 nonstall_intr_base = 0;
u64 nonstall_intr_mask = 0;
u32 active_engine_id, intr_mask;
/* Keep NV_PMC_INTR(1) disabled */
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
/*
* Enable nonstall interrupts in TOP
* Enable all engine specific non-stall interrupts in LEAF
*
* We need to read and add
* ctrl_legacy_engine_nonstall_intr_base_vectorid_r()
* to get correct interrupt id in NV_CTRL tree
*/
nonstall_intr_base = nvgpu_readl(g,
ctrl_legacy_engine_nonstall_intr_base_vectorid_r());
for (i = 0; i < g->fifo.num_engines; i++) {
active_engine_id = g->fifo.active_engines_list[i];
intr_mask = g->fifo.engine_info[active_engine_id].intr_mask;
nonstall_intr_mask |= U64(intr_mask) << U64(nonstall_intr_base);
}
nvgpu_func_writel(g,
func_priv_cpu_intr_top_en_set_r(
NV_CPU_INTR_SUBTREE_TO_TOP_IDX(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)),
BIT32(NV_CPU_INTR_SUBTREE_TO_TOP_BIT(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)));
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_en_set_r(
NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)),
u64_lo32(nonstall_intr_mask));
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_en_set_r(
NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)),
u64_hi32(nonstall_intr_mask));
}
void intr_tu104_mask(struct gk20a *g)
{
u32 size, reg, i;
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
size = func_priv_cpu_intr_top_en_clear__size_1_v();
for (i = 0; i < size; i++) {
reg = func_priv_cpu_intr_top_en_clear_r(i);
nvgpu_func_writel(g, reg, 0xffffffffU);
}
}
/* Enable all required interrupts */
void intr_tu104_enable(struct gk20a *g)
{
intr_tu104_stall_enable(g);
intr_tu104_nonstall_enable(g);
}
/* Return non-zero if nonstall interrupts are pending */
u32 intr_tu104_nonstall(struct gk20a *g)
{
u32 nonstall_intr_status;
u32 nonstall_intr_set_mask;
nonstall_intr_status =
nvgpu_func_readl(g, func_priv_cpu_intr_top_r(
NV_CPU_INTR_SUBTREE_TO_TOP_IDX(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)));
nonstall_intr_set_mask = BIT32(
NV_CPU_INTR_SUBTREE_TO_TOP_BIT(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE));
return nonstall_intr_status & nonstall_intr_set_mask;
}
/* pause all nonstall interrupts */
void intr_tu104_nonstall_pause(struct gk20a *g)
{
nvgpu_func_writel(g,
func_priv_cpu_intr_top_en_clear_r(
NV_CPU_INTR_SUBTREE_TO_TOP_IDX(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)),
BIT32(NV_CPU_INTR_SUBTREE_TO_TOP_BIT(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)));
}
/* resume all nonstall interrupts */
void intr_tu104_nonstall_resume(struct gk20a *g)
{
nvgpu_func_writel(g,
func_priv_cpu_intr_top_en_set_r(
NV_CPU_INTR_SUBTREE_TO_TOP_IDX(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)),
BIT32(NV_CPU_INTR_SUBTREE_TO_TOP_BIT(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)));
}
/* Handle and clear all nonstall interrupts */
u32 intr_tu104_isr_nonstall(struct gk20a *g)
{
u32 i;
u32 nonstall_intr_base = 0;
u64 nonstall_intr_mask = 0;
u32 nonstall_intr_mask_lo, nonstall_intr_mask_hi;
u32 intr_leaf_reg0, intr_leaf_reg1;
u32 active_engine_id, intr_mask;
u32 ops = 0;
intr_leaf_reg0 = nvgpu_func_readl(g,
func_priv_cpu_intr_leaf_r(
NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)));
intr_leaf_reg1 = nvgpu_func_readl(g,
func_priv_cpu_intr_leaf_r(
NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)));
nonstall_intr_base = nvgpu_readl(g,
ctrl_legacy_engine_nonstall_intr_base_vectorid_r());
for (i = 0; i < g->fifo.num_engines; i++) {
active_engine_id = g->fifo.active_engines_list[i];
intr_mask = g->fifo.engine_info[active_engine_id].intr_mask;
nonstall_intr_mask = U64(intr_mask) << U64(nonstall_intr_base);
nonstall_intr_mask_lo = u64_lo32(nonstall_intr_mask);
nonstall_intr_mask_hi = u64_hi32(nonstall_intr_mask);
if ((nonstall_intr_mask_lo & intr_leaf_reg0) != 0U ||
(nonstall_intr_mask_hi & intr_leaf_reg1) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "nonstall intr from engine %d",
active_engine_id);
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_r(
NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)),
nonstall_intr_mask_lo);
nvgpu_func_writel(g,
func_priv_cpu_intr_leaf_r(
NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)),
nonstall_intr_mask_hi);
ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE |
GK20A_NONSTALL_OPS_POST_EVENTS);
}
}
return ops;
}
/* Return non-zero if stall interrupts are pending */
u32 intr_tu104_stall(struct gk20a *g)
{
u32 mc_intr_0;
mc_intr_0 = mc_gp10b_intr_stall(g);
if (mc_intr_0 != 0U) {
return mc_intr_0;
}
if (g->ops.mc.is_intr_hub_pending != NULL) {
return g->ops.mc.is_intr_hub_pending(g, 0);
}
return 0;
}
/* Return true if HUB interrupt is pending */
bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
{
return g->ops.mm.mmu_fault_pending(g);
}
/* pause all stall interrupts */
void intr_tu104_stall_pause(struct gk20a *g)
{
mc_gp10b_intr_stall_pause(g);
g->ops.fb.disable_hub_intr(g);
}
/* resume all stall interrupts */
void intr_tu104_stall_resume(struct gk20a *g)
{
mc_gp10b_intr_stall_resume(g);
g->ops.fb.enable_hub_intr(g);
}
#define MAX_INTR_TOP_REGS (2U)
void intr_tu104_log_pending_intrs(struct gk20a *g)
{
bool pending;
u32 intr, i;
intr = intr_tu104_nonstall(g);
if (intr != 0U) {
nvgpu_info(g, "Pending nonstall intr=0x%08x", intr);
}
intr = mc_gp10b_intr_stall(g);
if (intr != 0U) {
nvgpu_info(g, "Pending stall intr=0x%08x", intr);
}
if (g->ops.mc.is_intr_hub_pending != NULL) {
pending = g->ops.mc.is_intr_hub_pending(g, 0);
if (pending) {
nvgpu_info(g, "Pending hub intr");
}
}
for (i = 0; i < MAX_INTR_TOP_REGS; i++) {
intr = nvgpu_func_readl(g,
func_priv_cpu_intr_top_r(i));
if (intr == 0U) {
continue;
}
nvgpu_info(g, "Pending TOP%d intr=0x%08x", i, intr);
}
}
void mc_tu104_fbpa_isr(struct gk20a *g)
{
u32 intr_fbpa, fbpas;
u32 i, num_fbpas;
intr_fbpa = gk20a_readl(g, mc_intr_fbpa_r());
fbpas = mc_intr_fbpa_part_mask_v(intr_fbpa);
num_fbpas = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS);
for (i = 0u; i < num_fbpas; i++) {
if ((fbpas & BIT32(i)) == 0U) {
continue;
}
g->ops.fb.handle_fbpa_intr(g, i);
}
}
void mc_tu104_ltc_isr(struct gk20a *g)
{
u32 ltc;
/* Go through all the LTCs explicitly */
for (ltc = 0; ltc < nvgpu_ltc_get_ltc_count(g); ltc++) {
g->ops.ltc.intr.isr(g, ltc);
}
}

66
drivers/gpu/nvgpu/common/mc/mc_tu104.h
View File

@@ -1,66 +0,0 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_MC_TU104_H
#define NVGPU_MC_TU104_H
#include <nvgpu/types.h>
#define NV_CPU_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32U)
#define NV_CPU_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32U)
#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(i) ((i)*2U)
#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(i) (((i)*2U) + 1U)
#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32U)
#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32U)
#define NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
#define NV_CPU_INTR_TOP_NONSTALL_SUBTREE 0U
struct gk20a;
void intr_tu104_leaf_en_set(struct gk20a *g, u32 leaf_reg_index,
u32 leaf_reg_bit);
void intr_tu104_leaf_en_clear(struct gk20a *g, u32 leaf_reg_index,
u32 leaf_reg_bit);
void intr_tu104_top_en_set(struct gk20a *g, u32 top_reg_index,
u32 top_reg_bit);
void intr_tu104_vector_en_set(struct gk20a *g, u32 intr_vector);
void intr_tu104_vector_en_clear(struct gk20a *g, u32 intr_vector);
bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector);
void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector);
void intr_tu104_mask(struct gk20a *g);
void intr_tu104_enable(struct gk20a *g);
u32 intr_tu104_stall(struct gk20a *g);
void intr_tu104_stall_pause(struct gk20a *g);
void intr_tu104_stall_resume(struct gk20a *g);
u32 intr_tu104_nonstall(struct gk20a *g);
void intr_tu104_nonstall_pause(struct gk20a *g);
void intr_tu104_nonstall_resume(struct gk20a *g);
u32 intr_tu104_isr_nonstall(struct gk20a *g);
bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
void intr_tu104_log_pending_intrs(struct gk20a *g);
void mc_tu104_fbpa_isr(struct gk20a *g);
void mc_tu104_ltc_isr(struct gk20a *g);
#endif /* NVGPU_MC_TU104_H */