nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: sec2: update sec2 interfaces

Browse Source 
update sec2 rtos interfaces to support next dgpu sec2 ucode.

JIRA NVGPU-5468

Change-Id: I534a6eded8a9525dc09e5f57e46bef36f1a4e81b
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352103
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
mkumbar
2020-05-28 13:48:34 +05:30
committed by Alex Waterman
parent 1c40ebe9b1
commit f0de6fa54a
2 changed files with 14 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -48,6 +48,12 @@ struct nv_sec2_acr_cmd_bootstrap_falcon {
/* ID to identify Falcon, ref FALCON_ID_<XYZ> */ /* ID to identify Falcon, ref FALCON_ID_<XYZ> */
u32 falcon_id; u32 falcon_id;
/* Falcon Instance bootstrapped by ACR */
u32 falcon_instance;
/* Mask of indexes of same falcon to be multi bootstrapped by ACR */
u32 falcon_Index_Mask;
}; };
#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET 0U #define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET 0U
@@ -83,6 +89,9 @@ struct nv_sec2_acr_msg_bootstrap_falcon {
/* Bootstrapped falcon ID by ACR */ /* Bootstrapped falcon ID by ACR */
u32 falcon_id; u32 falcon_id;
/* Falcon Instance bootstrapped by ACR */
u32 falcon_instance;
}; };
/* /*

5
drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -58,6 +58,9 @@ struct sec2_init_msg_sec2_init {
u32 nv_managed_area_offset; u32 nv_managed_area_offset;
u16 nv_managed_area_size; u16 nv_managed_area_size;
/* Unused, kept for the binary compatibility */
u8 rsvd_1[16];
u8 rsvd_2[16];
}; };
union nv_flcn_msg_sec2_init { union nv_flcn_msg_sec2_init {