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gpu: nvgpu: remove unused register and fields

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cleanup header for removal of czf_bypass and pd_max_batches support.

JIRA NVGPU-2967

Change-Id: I7a1d8dfeabb87e3653c70a560282f99ff4310ce7
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071070
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-03-12 15:39:27 -07:00
committed by mobile promotions
parent e8b6580953
commit f1c9c1ebc0
1 changed files with 1 additions and 21 deletions
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22
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1734,10 +1734,6 @@ static inline u32 gr_pd_ab_dist_cfg1_r(void)
{
return 0x004064c4U;
}
static inline u32 gr_pd_ab_dist_cfg1_max_batches_f(u32 v)
{
return (v & 0xffffU) << 0U;
}
static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
{
return 0xffffU;
@@ -4398,20 +4394,4 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
{
return U32(0xffU) << 0U;
}
static inline u32 gr_gpc0_prop_debug1_r(void)
{
return 0x00500400U;
}
static inline u32 gr_gpc0_prop_debug1_czf_bypass_f(u32 v)
{
return (v & 0x3U) << 14U;
}
static inline u32 gr_gpc0_prop_debug1_czf_bypass_m(void)
{
return U32(0x3U) << 14U;
}
static inline u32 gr_gpc0_prop_debug1_czf_bypass_init_v(void)
{
return 0x00000001U;
}
#endif