nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Fix devg_nvgpu_igpu process crash.

Browse Source 
As part of the negative test case we replace the ACR binaries with
corrupted one(by editing the binary in hex editor). The expectaion
was the process should log the error and exit properly but instead
the process crashed.

We have found the root cause and it was because we were trying to
flush a memory which was not allocated.

To mitigate this issue we added a checking condition to check if the
memory was allocated before flushing.

Bug 3670576

Change-Id: I6b510388fb913695210c791e2253c7514bb7a0a9
Signed-off-by: ht <ht@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2762276
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
ht
2022-08-17 10:22:46 +00:00
committed by mobile promotions
parent c07ac78d52
commit f46a3abfc6
1 changed files with 12 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/nvgpu/common/pmu/super_surface/super_surface.c
View File

@@ -216,15 +216,19 @@ u32 nvgpu_pmu_get_ss_msg_fbq_element_offset(struct gk20a *g,
void nvgpu_pmu_ss_fbq_flush(struct gk20a *g, struct nvgpu_pmu *pmu)
{
nvgpu_memset(g, nvgpu_pmu_super_surface_mem(g,
pmu, pmu->super_surface),
(u64)offsetof(struct super_surface, fbq.cmd_queues),
0x00, sizeof(struct nv_pmu_fbq_cmd_queues));
if (pmu->super_surface != NULL) {
if (nvgpu_mem_is_valid(nvgpu_pmu_super_surface_mem(g, pmu, pmu->super_surface))) {
nvgpu_memset(g, nvgpu_pmu_super_surface_mem(g,
pmu, pmu->super_surface),
(u64)offsetof(struct super_surface, fbq.cmd_queues),
0x00, sizeof(struct nv_pmu_fbq_cmd_queues));
nvgpu_memset(g, nvgpu_pmu_super_surface_mem(g,
pmu, pmu->super_surface),
(u64)offsetof(struct super_surface, fbq.msg_queue),
0x00, sizeof(struct nv_pmu_fbq_msg_queue));
nvgpu_memset(g, nvgpu_pmu_super_surface_mem(g,
pmu, pmu->super_surface),
(u64)offsetof(struct super_surface, fbq.msg_queue),
0x00, sizeof(struct nv_pmu_fbq_msg_queue));
}
}
}
void nvgpu_pmu_super_surface_deinit(struct gk20a *g, struct nvgpu_pmu *pmu,