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gpu: nvgpu: make PMU_CMD_FLAGS* U8 values

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These macros are for setting the 8 bit ctrl_flags member of the
pmu_hdr struct. Making these macros U8 fixes MISRA 10.3 violations for
implicit assignment of different types.

JIRA NVGPU-1008

Change-Id: I325c845b01aa044d08458b51409b04ef29699335
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966339
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2018-12-05 13:35:37 -05:00
committed by mobile promotions
parent 8fcdd9c287
commit f6a2b839cf
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
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@@ -109,10 +109,10 @@ typedef u8 flcn_status;
#define PMU_CMD_FLAGS_PMU_MASK (0xF0)
#define PMU_CMD_FLAGS_STATUS BIT(0)
#define PMU_CMD_FLAGS_INTR BIT(1)
#define PMU_CMD_FLAGS_EVENT BIT(2)
#define PMU_CMD_FLAGS_WATERMARK BIT(3)
#define PMU_CMD_FLAGS_STATUS BIT8(0)
#define PMU_CMD_FLAGS_INTR BIT8(1)
#define PMU_CMD_FLAGS_EVENT BIT8(2)
#define PMU_CMD_FLAGS_WATERMARK BIT8(3)
#define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1))