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gpu: nvgpu: code correction in gr ecc unit

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FECS_FEATURE_OVERRIDE_ECC bits for SM_L0_CACHE and SM_L1_CHACHE
need to be checked against NV_PGRAPH_PRI_FECS_FEATURE_OVERRIDE_ECC_1
register.
Correct the error of checking those bits against
NV_PGRAPH_PRI_FECS_FEATURE_OVERRIDE_ECC register.

Jira NVGPU-4095

Change-Id: I09737b83496f9e728e0b022bd6a4e75741bd0c49
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210429
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2019-10-02 17:53:32 -07:00
committed by Alex Waterman
parent 46362bb271
commit f73da1dfe5
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c
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@@ -136,6 +136,9 @@ void gv11b_ecc_detect_enabled_units(struct gk20a *g)
u32 fecs_feature_override_ecc =
nvgpu_readl(g,
gr_fecs_feature_override_ecc_r());
u32 fecs_feature_override_ecc_1 =
nvgpu_readl(g,
gr_fecs_feature_override_ecc_1_r());
if (opt_feature_fuses_override_disable) {
if (opt_ecc_en) {
@@ -162,7 +165,7 @@ void gv11b_ecc_detect_enabled_units(struct gk20a *g)
fecs_feature_override_ecc, opt_ecc_en);
/* SM ICACHE*/
gv11b_ecc_enable_smicache(g,
fecs_feature_override_ecc, opt_ecc_en);
fecs_feature_override_ecc_1, opt_ecc_en);
/* LTC */
gv11b_ecc_enable_ltc(g,
fecs_feature_override_ecc, opt_ecc_en);