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gpu: nvgpu: Fix Misra 15.7 Violations.

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Misra rule 15.7 requires if..else if statement to end with else.
The else should have either one side effect or a comment.
Added nvgpu_log_info to print debug info.

JIRA NVGPU-1484

Change-Id: I7432ee03337e71d59d37dcffb0fb0ce9718163e0
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965207
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2018-12-05 11:24:50 +05:30
committed by mobile promotions
parent 581847c804
commit f7febd1c7a
3 changed files with 10 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/therm/therm_gp106.c
View File

@@ -51,6 +51,8 @@ int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8)
} else if ((therm_temp_sensor_tsense_state_v(readval) &
therm_temp_sensor_tsense_state_shadow_v()) != 0U) {
nvgpu_err(g, "Reading temperature from SHADOWed sensor!");
} else {
nvgpu_log_info(g, "Finished reading temperature");
}
// Convert from F9.5 -> F27.5 -> F24.8.

4
drivers/gpu/nvgpu/gm20b/clk_gm20b.c
View File

@@ -1347,6 +1347,8 @@ long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate,
freq = gpc_pll_params.max_freq;
} else if (freq < gpc_pll_params.min_freq) {
freq = gpc_pll_params.min_freq;
} else {
nvgpu_log_info(g, "frequency within range");
}
tmp_pll = clk->gpc_pll;
@@ -1417,6 +1419,8 @@ static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq)
freq = gpc_pll_params.max_freq;
} else if (freq < gpc_pll_params.min_freq) {
freq = gpc_pll_params.min_freq;
} else {
nvgpu_log_info(g, "frequency within range");
}
if (freq != old_freq) {

5
drivers/gpu/nvgpu/pmgr/pmgrpmu.c
View File

@@ -47,7 +47,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
if ((msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_SET_OBJECT) &&
(msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_QUERY) &&
(msg->msg.pmgr.msg_type != NV_PMU_PMGR_MSG_ID_LOAD)) {
nvgpu_err(g, "unknow msg %x", msg->msg.pmgr.msg_type);
nvgpu_err(g, "unknown msg %x", msg->msg.pmgr.msg_type);
return;
}
@@ -80,6 +80,9 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
msg->msg.pmgr.load.flcnstatus);
return;
}
} else {
/*Will not hit this case due to check in the beginning itself*/
nvgpu_err(g, "unknown msg %x", msg->msg.pmgr.msg_type);
}
phandlerparams->success = 1;