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gpu: nvgpu: gk20a: MISRA rule 15.6 fixes

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MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed
by brackets. This patch adds brackets to single line if/else/loop blocks
in the gk20a directory.

JIRA NVGPU-775

Change-Id: Ic8c4d84f961392bf9a0841bdc654a37858a604d0
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011657
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Adeel Raza
2019-02-04 13:48:59 -08:00
committed by mobile promotions
parent e70ba2af19
commit f81c083766
3 changed files with 9 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/gk20a/fence_gk20a.c
View File

@@ -300,8 +300,9 @@ int gk20a_fence_from_syncpt(
struct gk20a_fence *f = fence_out;
gk20a_init_fence(f, &gk20a_syncpt_fence_ops, os_fence);
if (!f)
if (!f) {
return -EINVAL;
}
f->nvhost_dev = nvhost_dev;
f->syncpt_id = id;

3
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -3016,13 +3016,14 @@ void gk20a_dump_channel_status_ramfc(struct gk20a *g,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
if ((pbdma_syncpointb_op_v(syncpointb) == pbdma_syncpointb_op_wait_v())
&& (pbdma_syncpointb_wait_switch_v(syncpointb) ==
pbdma_syncpointb_wait_switch_en_v()))
pbdma_syncpointb_wait_switch_en_v())) {
gk20a_debug_output(o, "%s on syncpt %u (%s) val %u",
(status == 3 || status == 8) ? "Waiting" : "Waited",
pbdma_syncpointb_syncpt_index_v(syncpointb),
nvgpu_nvhost_syncpt_get_name(g->nvhost_dev,
pbdma_syncpointb_syncpt_index_v(syncpointb)),
pbdma_syncpointa_payload_v(syncpointa));
}
#endif
gk20a_debug_output(o, " ");

7
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -4681,8 +4681,9 @@ static inline bool is_valid_cyclestats_bar0_offset_gk20a(struct gk20a *g,
/* support only 24-bit 4-byte aligned offsets */
bool valid = !(offset & 0xFF000003U);
if (g->allow_all)
if (g->allow_all) {
return true;
}
/* whitelist check */
valid = valid &&
@@ -4711,8 +4712,10 @@ int gk20a_gr_handle_notify_pending(struct gk20a *g,
#if defined(CONFIG_GK20A_CYCLE_STATS)
/* GL will never use payload 0 for cycle state */
if ((ch->cyclestate.cyclestate_buffer == NULL) || (isr_data->data_lo == 0))
if ((ch->cyclestate.cyclestate_buffer == NULL) ||
(isr_data->data_lo == 0)) {
return 0;
}
nvgpu_mutex_acquire(&ch->cyclestate.cyclestate_buffer_mutex);