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gpu: nvgpu: maintain ctx buffers mappings separately from ctx mems

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In order to maintain separate mappings of GR TSG and global context
buffers for different subcontexts, we need to separate the memory
struct and the mapping struct for the buffers. This patch moves
the mappings of all GR ctx buffers to new structure
nvgpu_gr_ctx_mappings.

This will be instantiated per subcontext in the upcoming patches.

Summary of changes:
  1. Various context buffers were allocated and mapped separately.
     All TSG context buffers are now stored in gr_ctx->mem[] array
     since allocation and mapping is unified for them.
  2. Mapping/unmapping and querying the GPU VA of the context
     buffers is now handled in ctx_mappings unit. Structure
     nvgpu_gr_ctx_mappings in nvgpu_gr_ctx holds the maps.
     On ALLOC_OBJ_CTX this struct is instantiated and deleted
     on free_gr_ctx.
  3. Introduce mapping flags for TSG and global context buffers.
     This is to map different buffers with different caching
     attribute. Map all buffers as cacheable except
     PRIV_ACCESS_MAP, RTV_CIRCULAR_BUFFER, FECS_TRACE, GR CTX
     and PATCH ctx buffers. Map all buffers as privileged.
  4. Wherever VM or GPU VA is passed in the obj_ctx allocation
     functions, they are now replaced by nvgpu_gr_ctx_mappings.
  5. free_gr_ctx API need not accept the VM as mappings struct
     will hold the VM. mappings struct will be kept in gr_ctx.
  6. Move preemption buffers allocation logic out of
     nvgpu_gr_obj_ctx_set_graphics_preemption_mode.
  7. set_preemption_mode and gr_gk20a_update_hwpm_ctxsw_mode
     functions need update to ensure buffers are allocated
     and mapped.
  8. Keep the unit tests and documentation updated.

With these changes there is clear seggregation of allocation and
mapping of GR context buffers. This will simplify further change
to add multiple address spaces support. With multiple address
spaces in a TSG, subcontexts created after first subcontext
just need to map the buffers.

Bug 3677982

Change-Id: I3cd5f1311dd85aad1cf547da8fa45293fb7a7cb3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2712222
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2022-04-05 18:14:11 +05:30
committed by mobile promotions
parent 931e5f8220
commit f95cb5f4f8
49 changed files with 1645 additions and 1076 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
userspace/units/fifo/tsg/nvgpu-tsg.c
View File

@@ -622,10 +622,9 @@ done:
#define F_TSG_RELEASE_NO_RELEASE_HAL BIT(0)
#define F_TSG_RELEASE_GR_CTX BIT(1)
#define F_TSG_RELEASE_MEM BIT(2)
#define F_TSG_RELEASE_VM BIT(3)
#define F_TSG_RELEASE_ENG_BUFS BIT(4)
#define F_TSG_RELEASE_SM_ERR_STATES BIT(5)
#define F_TSG_RELEASE_LAST BIT(6)
#define F_TSG_RELEASE_ENG_BUFS BIT(3)
#define F_TSG_RELEASE_SM_ERR_STATES BIT(4)
#define F_TSG_RELEASE_LAST BIT(5)
static void stub_tsg_release(struct nvgpu_tsg *tsg)
@@ -640,7 +639,7 @@ static void stub_tsg_deinit_eng_method_buffers(struct gk20a *g,
}
static void stub_gr_setup_free_gr_ctx(struct gk20a *g,
struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx)
struct nvgpu_gr_ctx *gr_ctx)
{
stub[1].name = __func__;
stub[1].count++;
@@ -650,24 +649,32 @@ static void stub_gr_setup_free_gr_ctx(struct gk20a *g,
int test_tsg_release(struct unit_module *m,
struct gk20a *g, void *args)
{
struct nvgpu_gr_ctx_desc *gr_ctx_desc;
struct nvgpu_mem *gr_ctx_mem;
struct nvgpu_fifo *f = &g->fifo;
struct gpu_ops gops = g->ops;
struct nvgpu_tsg *tsg = NULL;
struct vm_gk20a vm;
u32 branches = 0U;
int ret = UNIT_FAIL;
struct nvgpu_mem mem;
u32 free_gr_ctx_mask =
F_TSG_RELEASE_GR_CTX|F_TSG_RELEASE_MEM|F_TSG_RELEASE_VM;
F_TSG_RELEASE_GR_CTX|F_TSG_RELEASE_MEM;
const char *labels[] = {
"no_release_hal",
"gr_ctx",
"mem",
"vm",
"eng_bufs",
"sm_err_states"
};
gr_ctx_desc = nvgpu_gr_ctx_desc_alloc(g);
if (!gr_ctx_desc) {
unit_return_fail(m, "failed to allocate memory");
}
nvgpu_gr_ctx_set_size(gr_ctx_desc, NVGPU_GR_CTX_CTX,
NVGPU_CPU_PAGE_SIZE);
for (branches = 0U; branches < F_TSG_RELEASE_LAST; branches++) {
if (!(branches & F_TSG_RELEASE_GR_CTX) &&
@@ -683,8 +690,9 @@ int test_tsg_release(struct unit_module *m,
tsg = nvgpu_tsg_open(g, getpid());
unit_assert(tsg != NULL, goto done);
unit_assert(tsg->gr_ctx != NULL, goto done);
unit_assert(tsg->gr_ctx->mem.aperture ==
APERTURE_INVALID, goto done);
gr_ctx_mem = nvgpu_gr_ctx_get_ctx_mem(tsg->gr_ctx, NVGPU_GR_CTX_CTX);
unit_assert(gr_ctx_mem->aperture == APERTURE_INVALID, goto done);
g->ops.tsg.release =
branches & F_TSG_RELEASE_NO_RELEASE_HAL ?
@@ -696,11 +704,8 @@ int test_tsg_release(struct unit_module *m,
}
if (branches & F_TSG_RELEASE_MEM) {
nvgpu_dma_alloc(g, NVGPU_CPU_PAGE_SIZE, &mem);
tsg->gr_ctx->mem = mem;
}
if (branches & F_TSG_RELEASE_VM) {
ret = nvgpu_gr_ctx_alloc_ctx_buffers(g, gr_ctx_desc, tsg->gr_ctx);
unit_assert(ret == UNIT_SUCCESS, goto done);
tsg->vm = &vm;
/* prevent nvgpu_vm_remove */
nvgpu_ref_init(&vm.ref);
@@ -734,7 +739,7 @@ int test_tsg_release(struct unit_module *m,
gops.gr.setup.free_gr_ctx;
if (branches & F_TSG_RELEASE_MEM) {
nvgpu_dma_free(g, &mem);
nvgpu_gr_ctx_free_ctx_buffers(g, tsg->gr_ctx);
}
if (tsg->gr_ctx != NULL) {

10
userspace/units/fifo/tsg/nvgpu-tsg.h
View File

@@ -177,17 +177,19 @@ int test_tsg_unbind_channel(struct unit_module *m,
* - Check that in_use is false.
* - Check de-allocation of other resources:
* - Case where g->ops.gr.setup.free_gr_ctx is called.
* It requires dummy vm, gr_ctx and gr_ctx->mem to be allocated.
* It requires dummy vm, gr_ctx and gr_ctx->mem[NVGPU_GR_CTX_CTX] to be
* allocated.
* A stub is used to check that the HAL was actually invoked.
* - Other combinations of vm, gr_ctx and gr_ctx->mem allocations, to
* check that g->ops.gr.setup.free_gr_ctx is not called.
* - Other combinations of vm, gr_ctx and gr_ctx->mem[NVGPU_GR_CTX_CTX]
* allocations, to check that g->ops.gr.setup.free_gr_ctx is not called.
* - Unhook of event_ids (by adding 2 dummy events in event_id list, and
* checking that list is empty after TSG release).
* - Case where event_id is empty before TSG release is tested as well
* - Check that VM refcount is decremented (and VM deallocated in our
* case), when present.
* - Check that sm_error_states is deallocated.
* - Check any combination of VM, gr_ctx, gr_ctx->mem, and sm_error_state.
* - Check any combination of VM, gr_ctx, gr_ctx->mem[NVGPU_GR_CTX_CTX], and
* sm_error_state.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/

203
userspace/units/gr/ctx/nvgpu-gr-ctx.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,6 +31,7 @@
#include <nvgpu/dma.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/ctx.h>
#include <nvgpu/gr/ctx_mappings.h>
#include <nvgpu/posix/posix-fault-injection.h>
#include <nvgpu/posix/dma.h>
@@ -43,6 +44,37 @@
#define DUMMY_SIZE 0xF0U
static u64 nvgpu_gmmu_map_locked_stub(struct vm_gk20a *vm,
u64 vaddr,
struct nvgpu_sgt *sgt,
u64 buffer_offset,
u64 size,
u32 pgsz_idx,
u8 kind_v,
u32 ctag_offset,
u32 flags,
enum gk20a_mem_rw_flag rw_flag,
bool clear_ctags,
bool sparse,
bool priv,
struct vm_gk20a_mapping_batch *batch,
enum nvgpu_aperture aperture)
{
return 1;
}
static void nvgpu_gmmu_unmap_locked_stub(struct vm_gk20a *vm,
u64 vaddr,
u64 size,
u32 pgsz_idx,
bool va_allocated,
enum gk20a_mem_rw_flag rw_flag,
bool sparse,
struct vm_gk20a_mapping_batch *batch)
{
return;
}
int test_gr_ctx_error_injection(struct unit_module *m,
struct gk20a *g, void *args)
{
@@ -51,12 +83,22 @@ int test_gr_ctx_error_injection(struct unit_module *m,
struct vm_gk20a *vm;
struct nvgpu_gr_ctx_desc *desc;
struct nvgpu_gr_global_ctx_buffer_desc *global_desc;
struct nvgpu_gr_ctx_mappings *mappings = NULL;
struct nvgpu_gr_ctx *gr_ctx = NULL;
struct nvgpu_posix_fault_inj *dma_fi =
nvgpu_dma_alloc_get_fault_injection();
struct nvgpu_posix_fault_inj *kmem_fi =
nvgpu_kmem_get_fault_injection();
u64 low_hole = SZ_4K * 16UL;
struct nvgpu_channel *channel = (struct nvgpu_channel *)
malloc(sizeof(struct nvgpu_channel));
struct nvgpu_tsg *tsg = (struct nvgpu_tsg *)
malloc(sizeof(struct nvgpu_tsg));
u32 i;
if (channel == NULL || tsg == NULL) {
unit_return_fail(m, "failed to allocate channel/tsg");
}
desc = nvgpu_gr_ctx_desc_alloc(g);
if (!desc) {
@@ -84,68 +126,70 @@ int test_gr_ctx_error_injection(struct unit_module *m,
unit_return_fail(m, "nvgpu_vm_init failed\n");
}
/* Try to free gr_ctx before it is allocated. */
nvgpu_gr_ctx_free(g, gr_ctx, NULL, NULL);
channel->g = g;
channel->vm = vm;
gr_ctx = nvgpu_alloc_gr_ctx_struct(g);
if (!gr_ctx) {
unit_return_fail(m, "failed to allocate memory");
}
/* Context size is not set, so should fail. */
err = nvgpu_gr_ctx_alloc(g, gr_ctx, desc, vm);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
/* Set the size now, but inject dma allocation failures. */
nvgpu_gr_ctx_set_size(desc, NVGPU_GR_CTX_CTX, DUMMY_SIZE);
nvgpu_posix_enable_fault_injection(dma_fi, true, 0);
err = nvgpu_gr_ctx_alloc(g, gr_ctx, desc, vm);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
/* Inject kmem alloc failures to trigger mapping failures */
nvgpu_posix_enable_fault_injection(dma_fi, false, 0);
nvgpu_posix_enable_fault_injection(kmem_fi, true, 1);
err = nvgpu_gr_ctx_alloc(g, gr_ctx, desc, vm);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
/* Successful allocation */
nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
err = nvgpu_gr_ctx_alloc(g, gr_ctx, desc, vm);
if (err != 0) {
unit_return_fail(m, "failed to allocate context");
}
/* Try to free patch context before it is allocated. */
nvgpu_gr_ctx_free_patch_ctx(g, vm, gr_ctx);
/* Inject allocation error and allocate patch context */
nvgpu_gr_ctx_set_size(desc, NVGPU_GR_CTX_PATCH_CTX, DUMMY_SIZE);
nvgpu_posix_enable_fault_injection(dma_fi, true, 0);
err = nvgpu_gr_ctx_alloc_patch_ctx(g, gr_ctx, desc, vm);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
/* Successful allocation */
nvgpu_posix_enable_fault_injection(dma_fi, false, 0);
err = nvgpu_gr_ctx_alloc_patch_ctx(g, gr_ctx, desc, vm);
if (err != 0) {
unit_return_fail(m, "failed to allocate patch context");
}
g->ops.mm.gmmu.map = nvgpu_gmmu_map_locked_stub;
g->ops.mm.gmmu.unmap = nvgpu_gmmu_unmap_locked_stub;
global_desc = nvgpu_gr_global_ctx_desc_alloc(g);
if (!global_desc) {
unit_return_fail(m, "failed to allocate desc");
}
err = nvgpu_gr_ctx_map_global_ctx_buffers(g, gr_ctx, global_desc,
vm, false);
/* Try to free gr_ctx before it is allocated. */
nvgpu_gr_ctx_free(g, gr_ctx, NULL);
gr_ctx = nvgpu_alloc_gr_ctx_struct(g);
if (!gr_ctx) {
unit_return_fail(m, "failed to allocate memory");
}
tsg->gr_ctx = gr_ctx;
mappings = nvgpu_gr_ctx_alloc_or_get_mappings(g, tsg, vm);
if (mappings == NULL) {
unit_return_fail(m, "failed to allocate gr_ctx mappings");
}
/* Context size is not set, so should fail. */
err = nvgpu_gr_ctx_alloc_ctx_buffers(g, desc, gr_ctx);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
/* Set the size now, but inject dma allocation failures. */
nvgpu_gr_ctx_set_size(desc, NVGPU_GR_CTX_CTX, DUMMY_SIZE);
nvgpu_gr_ctx_set_size(desc, NVGPU_GR_CTX_PATCH_CTX, DUMMY_SIZE);
for (i = 0; i < 2; i++) {
nvgpu_posix_enable_fault_injection(dma_fi, true, i);
err = nvgpu_gr_ctx_alloc_ctx_buffers(g, desc, gr_ctx);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
nvgpu_posix_enable_fault_injection(dma_fi, false, 0);
}
err = nvgpu_gr_ctx_alloc_ctx_buffers(g, desc, gr_ctx);
if (err != 0) {
unit_return_fail(m, "unexpected success");
}
/* Inject kmem alloc failures to trigger mapping failures */
for (i = 0; i < 2; i++) {
nvgpu_posix_enable_fault_injection(kmem_fi, true, 2 * i);
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx,
global_desc, mappings, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
}
/* global ctx_desc size is not set. */
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, global_desc,
mappings, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
@@ -164,42 +208,21 @@ int test_gr_ctx_error_injection(struct unit_module *m,
unit_return_fail(m, "failed to allocate global buffers");
}
/* Fail global circular buffer mapping */
nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
err = nvgpu_gr_ctx_map_global_ctx_buffers(g, gr_ctx, global_desc,
vm, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
/* Fail global ctx buffer mappings */
for (i = 0; i < 4; i++) {
nvgpu_posix_enable_fault_injection(kmem_fi, true, 4 + (2 * i));
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, global_desc,
mappings, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
}
/* Fail global attribute buffer mapping */
nvgpu_posix_enable_fault_injection(kmem_fi, true, 4);
err = nvgpu_gr_ctx_map_global_ctx_buffers(g, gr_ctx, global_desc,
vm, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
/* Fail global pagepool buffer mapping */
nvgpu_posix_enable_fault_injection(kmem_fi, true, 8);
err = nvgpu_gr_ctx_map_global_ctx_buffers(g, gr_ctx, global_desc,
vm, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
/* Fail global access map buffer mapping */
nvgpu_posix_enable_fault_injection(kmem_fi, true, 12);
err = nvgpu_gr_ctx_map_global_ctx_buffers(g, gr_ctx, global_desc,
vm, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
}
/* Successful mapping */
nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
err = nvgpu_gr_ctx_map_global_ctx_buffers(g, gr_ctx, global_desc,
vm, false);
err = nvgpu_gr_ctx_mappings_map_gr_ctx_buffers(g, gr_ctx, global_desc,
mappings, false);
if (err != 0) {
unit_return_fail(m, "failed to map global buffers");
}
@@ -225,11 +248,9 @@ int test_gr_ctx_error_injection(struct unit_module *m,
nvgpu_gr_ctx_patch_write_end(g, gr_ctx, true);
/* cleanup */
nvgpu_gr_ctx_free_patch_ctx(g, vm, gr_ctx);
nvgpu_gr_ctx_free(g, gr_ctx, global_desc, vm);
nvgpu_gr_ctx_free(g, gr_ctx, global_desc);
nvgpu_free_gr_ctx_struct(g, gr_ctx);
nvgpu_gr_ctx_desc_free(g, desc);
nvgpu_vm_put(vm);
nvgpu_vm_put(g->mm.bar1.vm);
return UNIT_SUCCESS;

10
userspace/units/gr/ctx/nvgpu-gr-ctx.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,16 +40,15 @@ struct unit_module;
*
* Test Type: Feature, Error guessing
*
* Targets: #nvgpu_gr_ctx_alloc,
* Targets: #nvgpu_gr_ctx_alloc_ctx_buffers,
* #nvgpu_gr_ctx_free_ctx_buffers,
* #nvgpu_gr_ctx_free,
* #nvgpu_gr_ctx_desc_alloc,
* #nvgpu_gr_ctx_desc_free,
* #nvgpu_alloc_gr_ctx_struct,
* #nvgpu_free_gr_ctx_struct,
* #nvgpu_gr_ctx_set_size,
* #nvgpu_gr_ctx_alloc_patch_ctx,
* #nvgpu_gr_ctx_free_patch_ctx,
* #nvgpu_gr_ctx_map_global_ctx_buffers,
* #nvgpu_gr_ctx_mappings_map_global_ctx_buffers,
* #nvgpu_gr_ctx_patch_write_begin,
* #nvgpu_gr_ctx_patch_write,
* #nvgpu_gr_ctx_patch_write_end.
@@ -63,7 +62,6 @@ struct unit_module;
* - Inject dma allocation failure and try to allocate gr_ctx, should fail.
* - Inject kmem allocation failure and try to allocate gr_ctx, should fail.
* - Disable error injection and allocate gr_ctx, should pass.
* - Try to free patch_ctx before it is allocated, should fail.
* - Inject dma allocation failure and try to allocate patch_ctx, should fail.
* - Disable error injection and allocate patch_ctx, should pass.
* - Setup all the global context buffers.

4
userspace/units/gr/global_ctx/nvgpu-gr-global-ctx.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -100,7 +100,7 @@ int test_gr_global_ctx_alloc_error_injection(struct unit_module *m,
/* Ensure mapping fails before buffers are allocated */
gpu_va = nvgpu_gr_global_ctx_buffer_map(desc,
NVGPU_GR_GLOBAL_CTX_CIRCULAR, NULL, 0, false);
NVGPU_GR_GLOBAL_CTX_CIRCULAR, NULL, false);
if (gpu_va != 0) {
unit_return_fail(m, "unexpected success");
}

13
userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -757,17 +757,12 @@ int test_gr_init_hal_error_injection(struct unit_module *m,
}
nvgpu_gr_ctx_set_size(desc, NVGPU_GR_CTX_CTX, DUMMY_SIZE);
err = nvgpu_gr_ctx_alloc(g, gr_ctx, desc, vm);
nvgpu_gr_ctx_set_size(desc, NVGPU_GR_CTX_PATCH_CTX, DUMMY_SIZE);
err = nvgpu_gr_ctx_alloc_ctx_buffers(g, desc, gr_ctx);
if (err != 0) {
unit_return_fail(m, "failed to allocate context");
}
nvgpu_gr_ctx_set_size(desc, NVGPU_GR_CTX_PATCH_CTX, DUMMY_SIZE);
err = nvgpu_gr_ctx_alloc_patch_ctx(g, gr_ctx, desc, vm);
if (err != 0) {
unit_return_fail(m, "failed to allocate patch context");
}
/* global_ctx = false and arbitrary size */
g->ops.gr.init.commit_global_pagepool(g, gr_ctx, 0x12345678,
DUMMY_SIZE, false, false);
@@ -803,7 +798,7 @@ int test_gr_init_hal_error_injection(struct unit_module *m,
g->ops = gops;
/* cleanup */
nvgpu_gr_ctx_free_patch_ctx(g, vm, gr_ctx);
nvgpu_gr_ctx_free_ctx_buffers(g, gr_ctx);
nvgpu_free_gr_ctx_struct(g, gr_ctx);
nvgpu_gr_ctx_desc_free(g, desc);
nvgpu_vm_put(vm);

48
userspace/units/gr/obj_ctx/nvgpu-gr-obj-ctx.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -35,6 +35,7 @@
#include <nvgpu/gr/gr_utils.h>
#include <nvgpu/gr/subctx.h>
#include <nvgpu/gr/ctx.h>
#include <nvgpu/gr/ctx_mappings.h>
#include <nvgpu/gr/obj_ctx.h>
#include <nvgpu/posix/posix-fault-injection.h>
@@ -117,6 +118,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
struct nvgpu_gr_ctx_desc *desc;
struct nvgpu_gr_global_ctx_buffer_desc *global_desc;
struct nvgpu_gr_ctx *gr_ctx = NULL;
struct nvgpu_gr_ctx_mappings *mappings = NULL;
struct nvgpu_gr_subctx *subctx = NULL;
struct nvgpu_mem inst_block;
struct nvgpu_gr_config *config = nvgpu_gr_get_config_ptr(g);
@@ -128,6 +130,8 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
nvgpu_local_golden_image_get_fault_injection();
int (*init_sm_id_table_tmp)(struct gk20a *g,
struct nvgpu_gr_config *config);
struct nvgpu_tsg *tsg = (struct nvgpu_tsg *)
malloc(sizeof(struct nvgpu_tsg));
/* Inject allocation failures and initialize obj_ctx, should fail */
nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
@@ -171,6 +175,8 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
unit_return_fail(m, "failed to allocate memory");
}
tsg->gr_ctx = gr_ctx;
global_desc = nvgpu_gr_global_ctx_desc_alloc(g);
if (!global_desc) {
unit_return_fail(m, "failed to allocate desc");
@@ -195,10 +201,15 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
unit_return_fail(m, "failed to allocate subcontext");
}
mappings = nvgpu_gr_ctx_mappings_create(g, tsg, vm);
if (mappings == NULL) {
unit_return_fail(m, "failed to allocate gr_ctx mappings");
}
/* Fail gr_ctx allocation */
nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -207,7 +218,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
/* Fail patch_ctx allocation */
nvgpu_posix_enable_fault_injection(kmem_fi, true, 3);
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -216,7 +227,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
/* Fail circular buffer mapping */
nvgpu_posix_enable_fault_injection(kmem_fi, true, 8);
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -228,7 +239,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
g->ops.gr.init.fe_pwr_mode_force_on = test_fe_pwr_mode_force_on;
fe_pwr_mode_count = 0;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -237,7 +248,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
/* Fail second call to gops.gr.init.fe_pwr_mode_force_on */
fe_pwr_mode_count = 1;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -252,7 +263,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
g->ops.gr.falcon.ctrl_ctxsw = test_falcon_ctrl_ctxsw;
ctrl_ctxsw_count = -1;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -265,7 +276,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
g->ops.gr.init.wait_idle = test_gr_wait_idle;
gr_wait_idle_count = 2;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -278,7 +289,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
g->ops.gr.init.load_sw_bundle_init = test_load_sw_bundle;
load_sw_bundle_count = 0;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -288,7 +299,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
g->ops.gr.init.load_sw_veid_bundle = test_load_sw_bundle;
load_sw_bundle_count = 1;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -308,7 +319,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
g->ops.gr.init.wait_idle = test_gr_wait_idle;
gr_wait_idle_count = 4;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -323,7 +334,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
*/
ctrl_ctxsw_count = 1;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -335,7 +346,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
*/
ctrl_ctxsw_count = 2;
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -347,7 +358,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
/* Fail golden context verification */
nvgpu_posix_enable_fault_injection(golden_ctx_verif_fi, true, 0);
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -358,7 +369,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
/* Finally, successful obj_ctx allocation */
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err != 0) {
unit_return_fail(m, "failed to allocate obj_ctx");
@@ -371,14 +382,14 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
/* Reallocation with golden image already created */
err = nvgpu_gr_obj_ctx_alloc(g, golden_image, global_desc, desc,
config, gr_ctx, subctx, vm, &inst_block,
config, gr_ctx, subctx, mappings, &inst_block,
VOLTA_COMPUTE_A, 0, false, false);
if (err != 0) {
unit_return_fail(m, "failed to re-allocate obj_ctx");
}
/* Set preemption mode with invalid compute class */
err = nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(g, config, desc, gr_ctx, vm,
err = nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode(g, config, desc, gr_ctx,
VOLTA_DMA_COPY_A, 0, NVGPU_PREEMPTION_MODE_COMPUTE_CTA);
if (err == 0) {
unit_return_fail(m, "unexpected success");
@@ -386,8 +397,7 @@ int test_gr_obj_ctx_error_injection(struct unit_module *m,
/* Cleanup */
nvgpu_gr_subctx_free(g, subctx, vm);
nvgpu_gr_ctx_free_patch_ctx(g, vm, gr_ctx);
nvgpu_gr_ctx_free(g, gr_ctx, global_desc, vm);
nvgpu_gr_ctx_free(g, gr_ctx, global_desc);
nvgpu_free_gr_ctx_struct(g, gr_ctx);
nvgpu_gr_ctx_desc_free(g, desc);
nvgpu_gr_obj_ctx_deinit(g, golden_image);

3
userspace/units/gr/obj_ctx/nvgpu-gr-obj-ctx.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,7 +53,6 @@ struct unit_module;
* nvgpu_gr_subctx_free,
* nvgpu_gr_obj_ctx_commit_inst,
* nvgpu_gr_obj_ctx_commit_inst_gpu_va,
* nvgpu_gr_ctx_get_patch_ctx_mem,
* nvgpu_gr_subctx_get_ctx_header,
* nvgpu_gr_subctx_load_ctx_header,
* nvgpu_gr_global_ctx_get_size,

2
userspace/units/gr/setup/nvgpu-gr-setup.c
View File

@@ -584,7 +584,7 @@ static void gr_setup_fake_free_obj_ctx(struct unit_module *m, struct gk20a *g)
g->ops.gr.setup.free_subctx(gr_setup_ch);
nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
g->ops.gr.setup.free_gr_ctx(g, 0, 0);
g->ops.gr.setup.free_gr_ctx(g, NULL);
gr_setup_ch->subctx = gr_subctx;
}

2
userspace/units/gr/setup/nvgpu-gr-setup.h
View File

@@ -55,7 +55,7 @@ struct unit_module;
* nvgpu_gr_ctx_get_ctx_mem,
* nvgpu_gr_ctx_set_tsgid,
* nvgpu_gr_ctx_get_tsgid,
* nvgpu_gr_ctx_get_global_ctx_va,
* nvgpu_gr_ctx_mappings_get_global_ctx_va,
* gops_gr_setup.alloc_obj_ctx,
* nvgpu_gr_ctx_load_golden_ctx_image,
* gm20b_ctxsw_prog_set_patch_addr,