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gpu: nvgpu: disable hw error injection support in safety-release

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This patch disables HW based fake error injection support in safety-release
build. For this purpose, it makes use of the following flag:
CONFIG_NVGPU_INJECT_HWERR.

JIRA NVGPU-3861

Change-Id: I1fa8544e67adbc53a1f3b98b340d76cf4f5bf524
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163289
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2019-07-29 14:44:32 +05:30
committed by mobile promotions
parent 0e2a6ac44c
commit fa6ada7619
7 changed files with 19 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/Makefile
View File

@@ -50,6 +50,7 @@ ccflags-y += -DCONFIG_NVGPU_FALCON_DEBUG
ccflags-y += -DCONFIG_NVGPU_FALCON_NON_FUSA
ccflags-y += -DCONFIG_NVGPU_IOCTL_NON_FUSA
ccflags-y += -DCONFIG_NVGPU_COMMON_NON_FUSA
ccflags-y += -DCONFIG_NVGPU_INJECT_HWERR
ifeq ($(CONFIG_NVGPU_LOGGING),y)
ccflags-y += -DCONFIG_NVGPU_LOGGING=1

2
drivers/gpu/nvgpu/Makefile.shared.configs
View File

@@ -106,6 +106,8 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SYSFS
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_FALCON_DEBUG
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_INJECT_HWERR
#
# Flags enabled only for regular build profile.
#

2
drivers/gpu/nvgpu/hal/fb/intr/fb_intr_ecc_gv11b_fusa.c
View File

@@ -31,6 +31,7 @@
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_fb_intr_inject_hubmmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err,
u32 error_info)
@@ -100,6 +101,7 @@ gv11b_fb_intr_get_hubmmu_err_desc(struct gk20a *g)
return &hubmmu_err_desc;
}
#endif /* CONFIG_NVGPU_INJECT_HWERR */
static void gv11b_fb_intr_handle_ecc_l2tlb(struct gk20a *g, u32 ecc_status)
{

2
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c
View File

@@ -28,6 +28,7 @@
#include "ecc_gv11b.h"
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
@@ -333,6 +334,7 @@ gv11b_gr_intr_get_gcc_err_desc(struct gk20a *g)
return &gcc_err_desc;
}
#endif /* CONFIG_NVGPU_INJECT_HWERR */
static void gv11b_ecc_enable_smlrf(struct gk20a *g,
u32 fecs_feature_override_ecc, bool opt_ecc_en)

8
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -185,8 +185,10 @@ static void gv11b_init_gpu_characteristics(struct gk20a *g)
static const struct gpu_ops gv11b_ops = {
.ltc = {
#ifdef CONFIG_NVGPU_INJECT_HWERR
.get_ltc_err_desc =
gv11b_ltc_get_err_desc,
#endif /* CONFIG_NVGPU_INJECT_HWERR */
.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
.init_fs_state = gv11b_ltc_init_fs_state,
.flush = gm20b_flush_ltc,
@@ -290,6 +292,7 @@ static const struct gpu_ops gv11b_ops = {
.ecc = {
.detect = gv11b_ecc_detect_enabled_units,
.init = gv11b_ecc_init,
#ifdef CONFIG_NVGPU_INJECT_HWERR
.get_mmu_err_desc =
gv11b_gr_intr_get_mmu_err_desc,
.get_gcc_err_desc =
@@ -300,6 +303,7 @@ static const struct gpu_ops gv11b_ops = {
gv11b_gr_intr_get_gpccs_err_desc,
.get_fecs_err_desc =
gv11b_gr_intr_get_fecs_err_desc,
#endif /* CONFIG_NVGPU_INJECT_HWERR */
},
.ctxsw_prog = {
.hw_get_fecs_header_size =
@@ -705,8 +709,10 @@ static const struct gpu_ops gv11b_ops = {
.is_valid_compute = gv11b_class_is_valid_compute,
},
.fb = {
#ifdef CONFIG_NVGPU_INJECT_HWERR
.get_hubmmu_err_desc =
gv11b_fb_intr_get_hubmmu_err_desc,
#endif /* CONFIG_NVGPU_INJECT_HWERR */
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gv11b_fb_init_fs_state,
.set_mmu_page_size = NULL,
@@ -1076,8 +1082,10 @@ static const struct gpu_ops gv11b_ops = {
.elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
},
.pmu = {
#ifdef CONFIG_NVGPU_INJECT_HWERR
.get_pmu_err_desc =
gv11b_pmu_intr_get_err_desc,
#endif /* CONFIG_NVGPU_INJECT_HWERR */
/*
* Basic init ops are must, as PMU engine used by ACR to
* load & bootstrap GR LS falcons without LS PMU, remaining

2
drivers/gpu/nvgpu/hal/ltc/ltc_gv11b_fusa.c
View File

@@ -34,6 +34,7 @@
#include <nvgpu/utils.h>
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_ltc_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
@@ -89,6 +90,7 @@ struct nvgpu_hw_err_inject_info_desc * gv11b_ltc_get_err_desc(struct gk20a *g)
return &ltc_err_desc;
}
#endif /* CONFIG_NVGPU_INJECT_HWERR */
/*
* Sets the ZBC stencil for the passed index.

2
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c
View File

@@ -39,6 +39,7 @@
#define ALIGN_4KB 12
#ifdef CONFIG_NVGPU_INJECT_HWERR
int gv11b_pmu_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
@@ -86,6 +87,7 @@ gv11b_pmu_intr_get_err_desc(struct gk20a *g)
return &pmu_err_desc;
}
#endif /* CONFIG_NVGPU_INJECT_HWERR */
/* error handler */
void gv11b_clear_pmu_bar0_host_err_status(struct gk20a *g)