Nvgpu submit path has a lot of dependency on Linux framework
e.g. use of copy_from_user, use of structures defined in uapi/nvgpu headers,
dma_buf_* calls for trace support etc
Hence to keep common code independent of Linux code, move submit path to
Linux directory
Move below APIs to common/linux/channel.c
trace_write_pushbuffer()
trace_write_pushbuffer_range()
gk20a_submit_prepare_syncs()
gk20a_submit_append_priv_cmdbuf()
gk20a_submit_append_gpfifo()
gk20a_submit_channel_gpfifo()
Move below APIs to common/linux/ce2.c
gk20a_ce_execute_ops()
Define gk20a_ce_execute_ops() in common/linux/ce2.c, and declare it in
gk20a/ce2_gk20a.h since it is needed in common/mm code too
Each OS needs to implement this API separately
gk20a_channel_alloc_gpfifo() use sizeof(nvgpu_gpfifo) to get size of one gpfifo
entry, but structure nvgpu_gpfifo is linux specific
Define new nvgpu_get_gpfifo_entry_size() in linux specific code and use it
in gk20a_channel_alloc_gpfifo() to get gpfifo entry size
Each OS needs to implement this API separately
Export some APIs from gk20a/ce2_gk20a.h and gk20a/channel_gk20a.h that are
needed in linux code
Jira NVGPU-259
Jira NVGPU-313
Change-Id: I360c6cb8ce4494b1e50c66af334a2a379f0d2dc4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586277
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Split the ctxsw trace "core" API code into <nvgpu/ctxsw_trace.h>. This
is not perect though since there's some Linuxisms present in the HAL
and as such that code has to be hidden by the ctxsw tracing CONFIG. But
this patch should work for QNX such that it will allow the code to
build as long as CONFIG_GK20A_CTXSW_TRACE is not set.
Also fix the copywrite notice in the ctxsw code present under
common/linux to be GPL.
JIRA NVGPU-287
Change-Id: I94715864caf335b7220185492e4629d713b025e0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589429
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In current code vgpu only set error notifier for the reporting channel
but abort the whole tsg. When the tsg is aborted, all channels of the
tsg are supposed have had their error notifiers set. Set it for all
channels once any of the channels gets an MMU fault.
For now, RM server still reports num-of-channel times for tsg mmu fault.
We may optimize it in future.
Jira VFND-3798
Change-Id: I6deaca55e7420899af8eabec72ad888d2726ad3c
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588098
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove the buffer_attrs struct and replace it with a more
streamlined nvgpu_ctag_buffer_info struct. This struct allows
several different fields to all be passed by pointer to the
various kind/compression functions in the VM map process.
This path also moves several comptag/kind related functions
to the core vm.c code since these functions can be reused by
other OSes.
Change-Id: I2a0f0a1c4b554ce4c8f2acdbe3161392e717d3bf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583984
GVS: Gerrit_Virtual_Submit
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Remove the always true field 'user_mapped' from the mapped_buf
struct. All mapped_bufs are mapped by a user request since they
always originate from a dma_buf (for Linux, that is). As such
there is a fair amount of logic that could be deleted.
Linux specific: the own_mem_ref field was also be deleted. The
logic of only storing a dma_buf ref when the buffer is mapped
for the first time by a user is easy: when the mapped buffer is
found in the map cache release the outstanding dma_buf ref taken
earlier on in the map path. If the map cache does not have the
buffer simply let the higher level map code keep the dma_buf ref.
The dma_buf ref is released when the nvgpu_vm_unmap_system()
call-back is called by the unmap path.
JIRA NVGPU-30
JIRA NVGPU-71
Change-Id: I229d136713812a7332bdadd5ebacd85d983bbbf0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583983
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Re-organize the unmap code to be better split between OS specific
requirements and common core requirements. The new code flow works
as follows:
nvgpu_vm_unmap()
Is the primary entrance to the unmap path. It takes a VM and a GPU
virtual address to unmap. There's also an optional batch mapping
struct.
This function is responsible for making sure there is a real buffer
and that if it's being called on a fixed mapping then the mapping
will definitely be freed (since buffers are ref-counted). Then this
function decrements the ref-count and returns.
If the ref-count hits zero then __nvgpu_vm_unmap_ref() is called
which just calls __nvgpu_vm_unmap() with the relevant batch struct
if present. This is where the real work is done. __nvgpu_vm_unmap()
clears the GMMU mapping, removes the mapped buffer from the various
lists and trees it may be in and then calls the
nvgpu_vm_unmap_system() function. This function handles any OS
specific stuff and must be defined by all VM OS implementations.
There's a a short cut used by some other core VM code to free
mappings without going through nvgpu_vm_map(). Mostly they just
directly decrement the mapping ref-count which can then call
__nvgpu_vm_unmap_ref() if the ref-count hits zero.
JIRA NVGPU-30
JIRA NVGPU-71
Change-Id: Ic626d37ab936819841bab45214f027b40ffa4e5a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583982
Reviewed-by: Automatic_Commit_Validation_User
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TSG enable sequence in native has been modified due to a
hardware bug requiring enabling all channels with NEXT and
CTX_RELOAD set in a TSG, and then enabling rest of channels.
However it is not possible to check if NEXT and CTX_RELOAD
is set in vgpu. Have a separate implementation for enabling
tsg sequence in vgpu till the fix for hardware bug is
implemented for virtualized configuration.
Bug 200348087
Change-Id: I6bfc52138bc540c0ea0ad18a85155eeff6f9efa8
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588740
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Issue
Currently bitmask of engine indices is being saved.
This will give wrong active engine ids for a given runlist
and s/w will end up checking/polling wrong engine_status
registers as these registers are indexed by active
engine ids. Also reset_eng_bitmask will end up
having wrong value for active engine ids to be reset.
Details for runlists serving engines ids for gv11b are:-
runlist id 0: gr = 0, grcopy 0 = 2, grcopy1 = 3
runlist id 1: async ce = 1
Incorrect values
init_runlist:705 [DBG] runlist 0 : eng bitmask 7 (eng 0, 1, 2)
init_runlist:705 [DBG] runlist 1 : eng bitmask 8 (eng 3)
Fix
Save bitmask of active engine ids in runlist info.
Right value
init_runlist:705 [DBG] runlist 0 : eng bitmask d (eng 0, 2, 3)
init_runlist:705 [DBG] runlist 1 : eng bitmask 2 (eng 1)
Bug 200277163
Bug 1945121
Change-Id: Ia299aa0881c4a258080bb0daa3a542fef0d94e4f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584066
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gk20a/clk_gk20a.h is a common file but still includes linux specific headers
Clean them up as below
- put linux/clk-provider.h include under config CONFIG_COMMON_CLK
- move linux/clkdev.h include to common/linux/platform_gk20a_tegra.c as it is no
longer needed in this file
Jira NVGPU-259
Change-Id: I4f5b996d3dea91ec3d737d4caa45e0eff6a7ee74
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588220
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use nvgpu_alloc_obj_ctx_args structure specific to Linux code only.
Pass the fields of the structure as separate arguments to all common
functions.
gr_ops_gp10b.h referred to the struct, but it's not used anywhere,
so delete the file.
JIRA NVGPU-259
Change-Id: Idba78d48de1c30f205a42da2fe47a9f8c03735f1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586563
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Migrate ctxsw_trace_gk20a.c to common/linux/ctxsw_trace.c. This
has been done becasue the ctxsw tracing code is currently too
tightly tied to the Linux OS due to usage of a couple system calls:
- poll()
- mmap()
And general Linux driver framework code. As a result pulling the
logic out of the FECS tracing code is simply too large a scope for
time time being.
Instead the code was just copied as much as possible. The HAL ops
for the FECS code was hidden behind the FECS tracing config so
that the vm_area_struct is not used when QNX does not define said
config. All other non-HAL functions called by the FECS ctxsw
tracing code ha now also been hidden by this config. This is not
pretty but for the time being it seems like the way to go.
JIRA NVGPU-287
Change-Id: Ib880ab237f4abd330dc66998692c86c4507149c2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586547
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In gk20a_fifo_tsg_unbind_channel(), we always verify channel status before
unbinding a channel from TSG
But in case TSG has alread timed out we never re-enable it so it does not
make sense to inspect channel status anyways
So skip channel status verification in case TSG has timed out
Bug 200327095
Change-Id: Iccf601271290643c235c3f2656201549210a6886
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586015
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Native code for verifying tsg status on ctx reload is not
possible on vgpu. Unset gops->fifo.tsg_verify_status_faulted
operation for vgpu for now. This needs to be implemented
separately for vgpu later.
Bug 200348087
Change-Id: I73791401de1ce7b7f8644ea4f9ccae3fc51dc7aa
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585783
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Update all Kconfig files and Makefiles to rely on the kernel overlay
feature. In particular, don't include any Kconfig files or Makefiles
from other overlays. -I directives in CFLAGS are not yet cleaned up.
Bug 1978395
Change-Id: I449ed2f07949785f2dd90a6833f4d8cd1711519a
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566641
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We currently check that no job is pending before proceeding with
suspend. This prevents suspend, when we could simply disable and
preempt all channels. Moreover, pending jobs accounting is done
using pm_runtime usage count, which is not updated for GPUs with
pm_runtime disabled (e.g. vgpu).
Replaced the check on pm_runtime usage count, with a check on
gk20a handle usage count. Suspend is allowed when there is no
task inside a busy/idle sequence.
JIRA EVLR-1852
Change-Id: I79e71c8112182622dbd1c7c46cd84befa61a5c4d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1552348
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We currently check that engine is idle before proceeding with
suspend. This prevents suspend when we could simply disable and
preempt all channels. Moreover, doing such a check in virtualization
case, would require to query engine status from RM server, before
proceeding with suspend.
Removed check on engine idle for system suspend.
JIRA EVLR-1852
Change-Id: Ic6dc65af14b00f236db20038dfc04fa0928c1fe2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1552347
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Delte the Linux headers and make some modifications to get rid of the
minor compilation issues that resulted.
- Add <linux/iommu.h> to os_linux.h
- Delete #if 0 code that "flushed" a buffer in gr_gk20a.c
- Delete FLUSH_CPU_DCACHE() macro
- Move the cache flush definitions to <nvgpu/linux/vm.h>
and include this header in sim_gk20a.c. This file will
not be used by QNX so this should be fine.
- Add <linux/pci_ids.h> to gp106/bios_gp106.c and
gp106/mclk_gp106.c.
- Move function to common/linux/dmabuf.h since it is a
dmabuf related function and uses a struct device pointer
as an argument.
JIRA NVGPU-30
Change-Id: I11f56b98524c7fac3efa91b4686592130e5f8a46
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585510
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clk_gk20a.h is used for dGPU and iGPU clocks. Because in gm20b the
clocks are owned by nvgpu, it has references to Linux CCF. Protect
the references behind #ifdef CONFIG_COMMON_CLK to compile it out on
non-Linux platforms.
JIRA NVGPU-259
Change-Id: I6ff095de7acaf1f828897cf3416acfaf050f8b51
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586414
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add a sysfs node to allow root user to set PRI_FE_GFXP_WFI_TIMEOUT, for gp10b
only, in units of sysclk cycles. Store the set value in a variable, and write
the set value to register after GPU is un-railgated.
NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT is engine_reset after Bug 1623341.
Change default value to be specified in cycles, rather than time. This value
is almost the current value in cycles calculated each boot.
Bug 1932782
Change-Id: I0a4207e637cd1413a1be95abe2bcce3adccf76fa
Reviewed-on: https://git-master.nvidia.com/r/1540939
Signed-off-by: Jonathan McCaffrey <jmccaffrey@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1580999
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In gk20a_fifo_tsg_unbind_channel(), we disable/preempt TSG, unbind one channel
from TSG, and then re-enable rest of the channels in TSG
But it is possible that TSG has already timed out due to some error and is
already disabled
If we re-enable all channels in such case, it can cause random issues right
after re-enabling faulted channel
Hence do not re-enable TSG if it has timedout
Since we disable all channels of TSG if one channel encounters fatal error,
it is safe to assume that TSG has timed out if one channel has timed out
Bug 1958308
Bug 200327095
Change-Id: I958ca6a2b408ff1338f2e551a79c072f1e203eda
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585421
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Add max_css_buffer_size to gpu characteristics. In the virtual
case, the size of the cycle stats snapshot buffer is constrained
by the size of the mempool shared between the guest OS and the
RM server, so tools need to find out what is the maximum size
allowed.
In the native case, we return 0xffffffff to indicate
that the buffer size is unbounded (subject to memory availability),
in the virtual case we return the size of the mempool.
Also collapse native init_cyclestats functions to a single version,
as each chip had identical versions of the code.
JIRA ESRM-54
Bug 200296210
Change-Id: I71764d32c6e71a0d101bd40f274eaa4bea3e5b11
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578930
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- Clock arbiter has lot of linux dependent code
so moved clk_arb.c to common/linux folder &
clk_arb.h to include/nvgpu/clk_arb.h, this move
helps to unblock QNX.
- QNX must implement functions present
under clk_arb.h as needed.
JIRA NVGPU-33
Change-Id: I38369fafda9c2cb9ba2175b3e530e40d0c746601
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582473
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We right now initialize czf_bypass value in gr_gp10b_init_preemption_state()
which is run at every rail ungate
And that results in any user specified value through sysfs getting lost after
railgate
To fix this, move initialization of czf_bypass to gk20a_init_gr_setup_sw() so
that it gets initialized only once
Add new HAL g->ops.gr.init_czf_bypass to initialize same and define it for
gp10b/gp106/vgpu-gp10b
Bug 2008262
Change-Id: I80a38ef527c86e32c6d64d0626b867239db9ea51
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585224
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PMU response(intr callback for messages) can run faster
than the kthread posting commands to PMU.
This causes the PMU message callback to skip important pmu
state change(which happens just after the PMU command is posted).
Solution:
State change should be triggered from only inside the intr callback.
Other places can only update the pmu_state variable.
This change also adds error check to print in case command post fails.
JIRA GPUT19X-20
Change-Id: Ib0a4275440455342a898c93ea9d86c5822e039a7
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583577
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BAR1 test could occasionally fail when doing CPU write through userd
then reading back through BAR1. This is because nvgpu_smp_mb() only
guarantees ordering between cores.
Replaced with nvgpu_mb() to ensure the write will be visible to all
bus masters in the system.
JIRA EVLR-1959
Bug 200352099
Change-Id: Id002e73d135e0805fca2f153a6de77e210a7b226
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582928
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Move vm_priv.h to <nvgpu/linux/vm.h> and rename nvgpu_vm_map()
to nvgpu_vm_map_linux(). Also remove a redundant unmap function
from the unmap path. These changes are the beginning of reworking
the nvgpu Linux mapping and unmapping code.
The rest of this patch is just the necessary changes to use the
new map function naming and the new path to the Linux vm header.
Patch Series Goal
-----------------
There's two major goals for this patch series. Note that these
goals are not achieved in this patch. There will be subsequent
patches.
1. Remove all last vestiges of Linux code from common/mm/vm.c
2. Implement map caching in the common/mm/vm.c code
To accomplish this firstly the VM mapping code needs to have the
struct nvgpu_mapped_buf data struct be completely Linux free. That
means implementing an abstraction for this to hold the Linux stuff
that mapped buffers carry about (SGT, dma_buf). This is why the
vm_priv.h code has been moved: it will need to be included by the
<nvgpu/vm.h> header so that the OS specific struct can be pulled
into struct nvgpu_mapped_buf.
Next renaming the nvgpu_vm_map() to nvgpu_vm_map_linux() is in
preparation for adding a new nvgpu_vm_map() that handles the
map caching with nvgpu_mapped_buf. The mapping code is fairly
straight forward: nvgpu_vm_map does OS generic stuff; each OS
then calls this function from an nvgpu_vm_map_<OS>() or the like
that does any OS specific adjustments/management.
Freeing buffers is much more tricky however. The maps are all
reference counted since userspace does not track buffers and
expects us to handle this instead. Ugh! Since there's ref-counts
the free code will require a callback into the OS specific code
since the OS specific code cannot free a buffer directly. THis
make's the path for freeing a buffer quite convoluted.
JIRA NVGPU-30
JIRA NVGPU-71
Change-Id: I5e0975f60663a0d6cf0a6bd90e099f51e02c2395
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578896
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Move much of the remaining generic MM code to a new common location:
common/mm/mm.c. Also add a corresponding <nvgpu/mm.h> header. This
mostly consists of init and cleanup code to handle the common MM
data structures like the VIDMEM code, address spaces for various
engines, etc.
A few more indepth changes were made as well.
1. alloc_inst_block() has been added to the MM HAL. This used to be
defined directly in the gk20a code but it used a register. As a
result, if this register hypothetically changes in the future,
it would need to become a HAL anyway. This path preempts that
and for now just defines all HALs to use the gk20a version.
2. Rename as much as possible: global functions are, for the most
part, prepended with nvgpu (there are a few exceptions which I
have yet to decide what to do with). Functions that are static
are renamed to be as consistent with their functionality as
possible since in some cases function effect and function name
have diverged.
JIRA NVGPU-30
Change-Id: Ic948f1ecc2f7976eba4bb7169a44b7226bb7c0b5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574499
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move functions to query preemption type names to the user of the
function: ioctl_channel.c. This removes a dependency to
<uapi/linux/nvgpu.h> from gr_gk20a.h.
JIRA NVGPU-259
Change-Id: I6cafda986eb4659fcfc1b19eac77e43aaaeaec76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577248
Function to query interleave name depends on IOCTL flag definition.
Move that code to fifo_gk20a.c to remove Linux dependency in header.
Change-Id: I6d6a80e550bf30973b2be09febc2347890b77d25
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577249
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
