MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the result of a bitwise operation is used as
boolean in the controlling expression of if and loop statements.
Changed few enums into macros because they were used in bit-shift &
bitwise operations and MISRA rule 10.1 forbids the usage of signed
types in bit-shift & bitwise operations.
JIRA NVGPU-1020
Change-Id: Ibc81c1e951342a5faf422ea73d13ef583535b768
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1947852
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The clk module was using u8's and u32's for the regime ID. Since the
regime id is only a byte, just use u8's.
This eliminates MISRA rule 10.3 violations for implicit assignments to
different types.
JIRA NVGPU-1008
Change-Id: Id3d1394402b248818cf959b46cd48611755f6912
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946259
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the prototype parameter.
JIRA NVGPU-847
Change-Id: I980ca7ba8adc853de9c1b6f6c7e7b3e4ac12f88e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926980
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: Iafe7d72a6fd31543653e0e10e2d2e552b6c3514b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945286
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I36494e84ee6cd4a108e2a539f48f102e47e2f7f4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926820
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in clk by renaming
them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when
there is no keyword repetition between file name and directory or
'NVGPU_HEADER-NAME' when there is repetition.
JIRA NVGPU-1028
Change-Id: I5305066dffcfb03e3c99fb501e783dcc70765b11
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809069
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Currently, clock arbiter code is extensively using dgpu specific
implementation. This patch restructures the clk_arbiter code and moves
gp106 specific code into HAL. Following changes are made in this patch
1) clk_domain_get_f_points is now invoked via HAL for gp106 i.e.
g->ops.clk.clk_domain_get_f_points.
2) moved nvgpu_clk_arb_change_vf_point and other related static
functions to clk_arb_gp106.c.
3) Instead of only checking if get_arbiter_clk_domain is empty, a
check for support_clk_freq_controller is also added. This is to enable
the clk_arbiter based on support from both the OS and the chips.
Bug 2061372
Change-Id: I65b0a4e02145a86fbbfb420ed591b1fa3c86f6dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774279
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added vf change inject support for gv10x
- Updated clk_pmu_vf_inject() to fill required data
for pascal or volta vf change inject support
- Added new ctrl clk interface for gv10x clk domain list
- Added pmu interface for gv10x clk domain list &
vf change inject request
- Modified clk cmd, msg & RPC id's to match
with chips_a_23609936 branch
Bug 200399373
Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700746
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clk_pmu_freq_controller_load used the default mask and affected
all the clock frequency controllers (CFC) which had their bits
set in the mask. We wish to enable/disable the CFCs in isolation
through debugfs. So we add a parameter(bit_idx) to the function
which will help affect only one CFC at a time
JIRA DNVGPU-207
DEPENDS ON: <http://git-master/r/1563302>
Change-Id: I233f52158b4a987bcc058a425380983dbe53fac8
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563303
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JIRA DNVGPU-170
1) Add clock frequency controller VBIOS structure definitions
2) Parse VBIOS tables and build boardobj structures for clock frequency
controller.
3) send clock frequency controller data structures to PMU
4) implement public function to send load/unload command to pmu
to enable/disable clock frequency controller support
Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248209
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07)
Reviewed-on: http://git-master/r/1270897
GVS: Gerrit_Virtual_Submit
Modification of the ARBITER clocks to be P-State aware
Up to now the arbiter just considered the whole range
of the GPC and MCLK domains, which could end up on
illegal combinations of MCLK, GPC2CLK, and set the
SYSCLK and XBARCLK domains below their minimum VCO
The following has been implemented:
(1) Modified VF tables to add which PState are
supported on each point.
(2) Return and store the current PState on the
arbiter state.
(3) Modified logic to prevent illegal combinations of
MCLK and GPC2CLK.
(4) Modified logic to prevent setting VF points for
XBAR and SYS domains below VCO limits.
(5) Modified voltage calculation to account for increased
values of XBAR and SYS on some VF points.
(6) Modified arbiter clock target logic to prevent an
application that has not requested a particular VF point
to set target to default targets.
(7) Remove unnecesary mutexes from critical path
JIRA DNVGPU-182
JIRA DNVGPU-183
Change-Id: I3d1c30903278f848681b8da833a867835acc99bb
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1247937
(cherry picked from commit b8bcc07eb3b5b70ec1ee19ace237df99d6170138)
Reviewed-on: http://git-master/r/1268063
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
JIRA DNVGPU-143
The arbiter is charged with selecting the proper
frequencies when multiple applications submit
simultaneously clock change requests
On the current implementation, the arbiter guarantees
that the selected frequency will be always higher
or equal to the request, as long as the request is
in range.
The current code is not yet realtime friendly, as
requests are not pre-allocated.
Summary of changes:
(1) pstate/vf switch no longer selects boot frequency
(2) changed mclk code change to accept input freq
(3) added arbiter
(4) now a single session can submit concurrent requests
the last request is the one that applies for that
session
(5) modified locking mechanism to reduce lock contention
(6) Added callback to notify the arbiter that the VF
table has changed and is no longer valid (PMU/Thermals
must call this when VF table is invalid)
(7) changed internal API to work with MHz
(8) added debugfs for stats
Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239461
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267120
Reviewed-by: Automatic_Commit_Validation_User
Expose the currently hard coded boot frequency, which is at the same
time the max frequency. We use it for filling in GPU characteristics.
Bug 200251486
Change-Id: I3c0abb7a385a83f61b93ddfa857b982c850853e3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252906
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
JIRA DNVGPU-123
now a function can be called with GPC2CLK value
It will take care calculating slave clock values
and calling VF inject to program clock
Made programming of boot clock code to use this
newly created function.
Change-Id: I74de7e9d98e379e94175ed2d9745ce3ab6c70691
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1221976
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235056
JIRA DNVGPU-123
Function will copy possible clock points for
a given master clock domain to pointer passed.
pointer with NULL value and count of zero can be passed
to query number of clock points for a given domain so that
memory can be allocated and function called again to
fill clock points
Change-Id: Iec6206f23789980036be99793599e934bd221035
Reviewed-on: http://git-master/r/1218912
(cherry picked from commit 9219697bff1e12deb605325055a02a7b387996e9)
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1235055
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
JIRA DNVGPU-123
function was added to retrieve V for F or
F for V for a given clock domain.
Clock domain can be master or slave.
F or V can be intermediate point between two
successive V or F values in VF table.
VF table should be cached before calling this function.
A F value below Fmin will return Vmin.
F > Fmax will return error
A V value above Vmax wil return F max.
A V value below Vmin will return error.
Change-Id: I28b4e8647510c6933e9e1204cfff31d74616e11a
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1211234
(cherry-picked from commit 5b83b03f2454fbec8d49a064ed09b09c92d3e9fa)
Reviewed-on: http://git-master/r/1235054
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
