Commit Graph

4 Commits

Author SHA1 Message Date
Konsta Holtta
22341d1c3e gpu: nvgpu: reserve wpr from allocator
In addition to nonwpr_base address, allocate also the wpr_base that is
configured as wpr, in order to not overlap user allocations on that
area.

This patch adds just the wpr region's mem_desc field available. For
devices that use the wpr separately, the field is used for that alloc.

Jira DNVGPU-18

Change-Id: I4a7523f2af2379ee38bdd34cb8ca2d81360dff7b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1182873
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2016-07-19 21:02:22 -07:00
Mahantesh Kumbar
9b1bb51cf0 gpu: nvgpu: ACR interface update
- ACR interface update to support
 next GPU chip ACR boot
- Udpate falcon ID

JIRA DNVGPU-34

Change-Id: Ic9e5e1f9bd965dbb65b4feaadcf63e457b49263b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1161695
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-09 16:56:09 -07:00
Mahantesh Kumbar
b4c355d32c gpu: nvgpu: Add gm204/gm206 ACR BL supoort
Update ACR BL desc & support for ACR boot.

JIRA DNVGPU-10

Change-Id: Iced2e10695439b2e1b47835f5c3c8a5d274e4b1e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1155027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-05 15:34:50 -07:00
Mahantesh Kumbar
147330c2da gpu: nvgpu: move & rename acr_gm20b to acr_desc
acr_gm20b renamed to acr_desc to support
multiple gpu chips

JIRA DNVGPU-10

Change-Id: Ib3b38d5845043f026ddc365a682b7bb454463326
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1152401
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-05-26 16:06:30 -07:00