Commit Graph

5 Commits

Author SHA1 Message Date
Seema Khowala
4c4f45e7eb gpu: nvgpu: mc: fix MISRA violations
Rule 8.6
Rule 16.4
Rule 10.3
Rule 10.7

JIRA NVGPU-3382

Change-Id: Ie5a8bfefaabd351428745fa95a90f1aac91b1b55
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111576
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-06 13:15:54 -07:00
Philip Elcan
f63a9f9e49 gpu: nvgpu: create nvgpu.common.hal.func unit
Move chip specific func files to hal/func. Update Makefiles and include
directives to make new locations.

JIRA NVGPU-2036

Change-Id: If3d633a2cd71d531f3eafdd1f808b0fd3ee6a113
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102898
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-23 12:46:09 -07:00
Seema Khowala
66cb9495a5 gpu: nvgpu: move mmu_fault_pending ops out from mm
Moved
-mmu_fault_pending mm ops to is_mmu_fault_pending mc ops
-mmu_fault_pending fb ops to is_mmu_fault_pending fb.intr ops. This
is needed to check if mmu fault intr is pending for volta onwards.

Added
is_mmu_fault_pending fifo ops. This is needed to check if mmu fault
interrupt is pending for chips prior to volta

JIRA NVGPU-1313

Change-Id: Ie8e778387cd486cb19b18c4aee734c581dcd9229
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094895
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-11 22:25:01 -07:00
Seshendra Gadagottu
9c465d5fd5 gpu: nvgpu: move fb interrupt handling to fb intr sub-unit
Moved fb interrupt handling related code to fb intr sub-unit.

Moved following hals from fb hal to fb intr hal and renamed to:
void (*enable)(struct gk20a *g);
void (*disable)(struct gk20a *g);
void (*isr)(struct gk20a *g);

gk20a_readl/writel are replaced with nvgpu_read/writel.
Hals are populated with new function names and code is modified
to call new hals.

Moved ecc interrupt to gv11b_fb_intr_handle_ecc in a separate file:
fb_intr_ecc_gv11b.c/h

JIRA NVGPU-2034

Change-Id: I80c7110c902c4e082561cf7cbe65c20eb9acb661
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-09 15:35:16 -07:00
Seema Khowala
f07d933076 gpu: nvgpu: move chip specific mc to hal
Move chip specific mc code from common/mc to hal/mc.
Replace gk20a_readl/writel with nvgpu_readl/writel
Replace 0xFFFFFFFFU with U32_MAX hash define
Change local variable names to fix checkpatch errors/warnings
Change BUG to WARN
Move defines to header files
Create new defines for hard coded delays

JIRA NVGPU-2041

Change-Id: I3594121a81da37ef58c47e87c45e96441e4cf8c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085268
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-02 01:04:44 -07:00