Commit Graph

12 Commits

Author SHA1 Message Date
Tejal Kudav
5af8cedf05 gpu: nvgpu: Nvlink interrupt handling
Enable logging and error reporting for MIF, DLPL, and TLC blocks.
Configure the NVLIPT and IOCTRL interrupt registers to rollup
the MIF and TLC errors on the link-specific fatal line and the
DLPL interrupts on link-specific intr_a(fatal) line. Both
link_err_fatal and link_intr_a are rolled up to stall interrupt line.
In the handling ISR, clear the interrupt status registers and print
an error.
Move the interrupt handling HAL code to /common/hal.

JIRA NVGPU-4350
JIRA NVGPU-4351
JIRA NVGPU-5231
JIRA NVGPU-4354
JIRA NVGPU-4355
JIRA NVGPU-4356

Change-Id: I14812499caf506592f3ae84d6681d857730d31ff
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313221
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2020-12-15 14:13:28 -06:00
tkudav
029da0437e gpu: nvgpu: Correct SCP_CTL reg read command
The offsets in minion register manuals are relative to minion base
address. Update the read command to use minion read API instead of
nvgpu_readl().

Change-Id: I6c0e2c11992f69e2fdd9e16dde061c92a771eae0
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292959
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2020-12-15 14:13:28 -06:00
tkudav
26406a070d gpu: nvgpu: Hardcode nvlink speed to 20G
Xavier Chip Product POR was updated to 20G only. No more qual work 
happening for 16G. So we do not plan to support 16G. Now that we have
a single speed left, remove the code added to support nvlink speed from
VBIOS as it is redundant.

JIRA NVGPU-2964

Change-Id: Icd71ebb8271240818e36d40bf73c60f0c5beb6bf
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284175
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2020-12-15 14:13:28 -06:00
Tejal Kudav
9438286a62 gpu: nvgpu: Add support for encrypted minion bin
Minion Ucode is enabling HS Ucode Encyrption. Minion Ucode builds
will put out separate Debug-signed and Prod-signed Encrypted image
files. The driver will load prod image or debug image depending
on the setting of DEBUG fuse setting.
Add support to read the SCP_CTL_STAT register to differentiate
debug and prod boards and load correct binary accordingly.
Update the binary name to support two minion ucodes binaries in
the build.

JIRA NVLINK-283
Bug 2701677

Change-Id: I5348e9705708eeab4ce639b0721f10882d8970a7
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258097
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2020-12-15 14:10:29 -06:00
Scott Long
3c7cf8b75a gpu: nvgpu: fix MISRA 10.5 issue in timeout code
This change switches nvgpu_timeout_peek_expired() to return a bool
instead of an int to remove advisory rule MISRA 10.5 violations.

MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.

JIRA NVGPU-3798

Change-Id: I5cf9badaf07493e11a639e47ae4cf221700134ff
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155617
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2019-07-24 17:04:38 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
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2019-06-11 09:46:24 -07:00
Vedashree Vidwans
54e179ddad gpu: nvgpu: fix MISRA 13.5 nvgpu.hal.nvlink
MISRA rule 13.5 doesn't allow right-hand operand of logical && or ||
operator to have persistent side effects. The reason is right-hand
operand is executed or checked depending on the left-hand operand value.
That means side effects in the right-hand operand may or may not occur,
contrary to programmer's expectation. Hence, this rule is implemented to
avoid unexpected behavior.

This patch divides if condition with logical && operator to nested if
conditions to resolve this violation.

Jira NVGPU-3277

Change-Id: I9f4387d71427821278db6bbda2eb53bd4d8ea543
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119684
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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2019-05-16 15:16:00 -07:00
Seema Khowala
b7835b5ead gpu: nvgpu: polling loops should not use gr idle timeouts
Rename GR_IDLE_CHECK_DEFAULT to POLL_DELAY_MIN_US
Rename GR_IDLE_CHECK_MAX to POLL_DELAY_MAX_US

JIRA NVGPU-1313

Change-Id: I1f645cbbc49298f9afdeb3a3d5e61a75d11b7c25
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083167
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2019-03-28 16:07:59 -07:00
Seema Khowala
a8587d5ee3 gpu: nvgpu: rename gr_idle_timeout_default to poll_timeout_default
Rename gr_idle_timeout_default to poll_timeout_default

Rename NVGPU_DEFAULT_GR_IDLE_TIMEOUT to
NVGPU_DEFAULT_POLL_TIMEOUT_MS

Rename gk20a_get_gr_idle_timeout to nvgpu_get_poll_timeout

JIRA NVGPU-1313

Change-Id: I17314f0fa4a386f806f6940073649a9082ee21ad
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083130
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2019-03-28 16:07:45 -07:00
Tejal Kudav
6a315a5a6d gpu: nvgpu: Add nvlink link_mode_transition unit
Move code used for transitioning between link and sublink modes
into a separate unit called 'link_mode_transition' under subelement
'nvlink'.
Also aggregate all the link/sublink mode related ops under
g->ops.nvlink.link_mode_transitions.

JIRA NVGPU-2862

Change-Id: I289faa10fd1c83b6b8d028b44fe244531ca42b15
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2035794
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2019-03-18 15:45:31 -07:00
Sagar Kamble
f4174ef048 gpu: nvgpu: move nvgpu_falcon struct to nvgpu/falcon.h
This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.

JIRA NVGPU-1993

Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069688
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2019-03-15 02:24:49 -07:00
Tejal Kudav
a6f0ce7971 gpu: nvgpu: Add nvlink "minion" unit
Move the code involved in dealing with minion into a separate unit
called "nvlink_minion". This unit includes minion HW access, ucode
handling, exposing state of minion and also dealing with minion
interrupts. The interfaces to this unit are partially exposed using
g->ops.nvlink.minion ops and rest are part of nvlink_minion.h public
header.

JIRA NVGPU-2860

Change-Id: Iea9288ea5f0b26688540b1eb8ab64afd756941a4
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030103
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2019-03-12 11:44:59 -07:00