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4189 Commits

Author SHA1 Message Date
Mahantesh Kumbar
15d5edab4a gpu: nvgpu: GPU_NEXT PMU ucode version update 
- Enable ECC interrupt in Falcon interrupt source
- Enable routing of ECC interrupt to HOST.

code CL: https://git-master.nvidia.com/r/#/c/1758176/
p4 CL# 24408680

Change-Id: Ib43c80be64e29ccbc6b19168e67ac6f4d200b2d8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1758175
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-07-02 11:13:35 -07:00
Terje Bergstrom
6ea52c59b0 gpu: nvgpu: Implement common nvgpu_mem_rd* functions 
nvgpu_mem_rd*() functions were implemented per OS. They also used
nvgpu_pramin_access_batched() and implemented a big portion of logic
for using PRAMIN in OS specific code.

Make the implementation for the functions generic. Move all PRAMIN
logic to PRAMIN and simplify the interface provided by PRAMIN.

Change-Id: I1acb9e8d7d424325dc73314d5738cb2c9ebf7692
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1753708
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-07-02 10:19:19 -07:00
Vishruth
cf2ac655fd gpu: nvgpu: fix missing max frequency 
The last frequency in the local array with all frequencies was missed
as the index was used as count. This caused max frequency to be not
listed among available frequencies, when few frequencies were
configured in BPMPFW-DT.

Bug 200381453

Change-Id: I72d000ed1842c41555f2de36209fa4e12188c325
Signed-off-by: Vishruth <vishruthj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1767642
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-07-02 08:06:45 -07:00
Thomas Fleury
ead0dfaaa3 gpu: nvgpu: make sure gpc2clk is greater than DVCO min 
For V/f point with gpc2clk exactly equal to DVCO min, we observe lower
than expected effective clock. Make sure min frequency for gpc2clk is
greater than DVCO min.

Bug 200412996

Change-Id: I85c33852c56c7a642aa5c85987d2da4147e73c22
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1764923
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-07-01 07:03:07 -07:00
Thomas Fleury
1691c34a68 gpu: nvgpu: adjust gpc2clk to nearest V/f point 
When requesting a gpc2clck below lowest V/f point, clock arbiter
did not properly adjust target value to nearest V/f point. This
could lead to lower than expected effective frequency. Fixed the
logic to adjust to nearest V/f point.

Bug 200412996

Change-Id: I36c24b4c081931e2ac54da14d49e46fcb14503e3
(cherry picked from commit 7ed1f8fb39f76208922daa91d00905cdb96b2304)
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1763641
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-07-01 07:03:03 -07:00
Konsta Holtta
cd7c433145 gpu: nvgpu: remove gk20a_channel_sync::incr_wfi 
This explicit incr_wfi has not been used since commit 06be77da37
("gpu: nvgpu: Do not send WFI when finishing channel").

Change-Id: I0213b0f728f83b483a7dbbef252912555b06815f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1765407
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-29 12:58:17 -07:00
Alex Waterman
65e4f3de09 gpu: nvgpu: Move the unlock in nvgpu_vm_area_free again 
Move the lock release to cover the g->ops.mm.gmmu_unmap() call
as well since this too must be called under the VM lock.

Bug 2156667

Change-Id: I17d819d1341e211a3d0bd0ecb7cf09884eaca767
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1764598
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-29 12:58:09 -07:00
Konsta Holtta
0aee2bc9fb gpu: nvgpu: remove legacy comment note 
gk20a_channel_clean_up_jobs hasn't needed a barrier since commit
d20a501dcb ("gpu: nvgpu: simplify job semaphore release in abort").

Bug 200327089

Change-Id: I64b9e3b7970de232ac553f570b8fd41aec3b7e21
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1764309
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-29 12:58:01 -07:00
Vishruth
646611cde4 gpu: nvgpu: filter frequencies only when required 
the logic used for selecting frequencies from achievable frequencies
of the GPU clk is selecting one in a set of 8 frequencies.
This reduces the number of available frequencies when the number of
achievable frequencies is small. Change this implementation to choose
all frequencies when the achievable frequency list is small.

Bug 200381453

Change-Id: Ib280d7ccf9b75f88f6c7c6d2666f05e92a0343bd
Signed-off-by: Vishruth <vishruthj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1753289
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-29 05:46:10 -07:00
Deepak Nibade
0a939d12f4 gpu: nvgpu: use explicit phys address for pci simulation 
nvgpu_mem_get_addr() gets virtual/phys address depending on the platform.
But we need to explicitly use physical addresses to configure PCI simulation
support since simulator expects physical address only

Hence use nvgpu_mem_get_phys_addr() explicitly to configure msg/send/recv
buffers needed for pci simulation support

Jira NVGPUT-41

Change-Id: I6870feef35fe81d43189fa048dc2f7052926bcc4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-29 04:49:58 -07:00
Alex Waterman
e323f562b2 gpu: nvgpu: Keep lock while unreffing mappings 
In the vm_area free code, when unreffing the mappings owned by
the vm_area, we need to continue holding the VM lock.

Also add a comment specifying this requirement in the VM code.

Bug 2156667

Change-Id: If0b430f045e4c585fcba2d3176163e5b19be8326
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1763235
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 11:14:04 -07:00
Konsta Holtta
e8d51f0c32 gpu: nvgpu: remove nvgpu_mem_{begin,end}() 
The NVGPU_DMA_NO_KERNEL_MAPPING flag is going away, and these functions
are no longer used. Delete them.

Change-Id: I0084d64c92783dd65306871e5cf6bd6366087caf
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761581
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 11:13:53 -07:00
Konsta Holtta
dc1e91a2d7 gpu: nvgpu: don't nvgpu_mem_{begin,end}() sim bufs 
nvgpu_dma_alloc_sys() gives cpu-mapped memory by default. Remove the
explicit calls to map and unmap the sim buffers.

Change-Id: Icf71961c16a8b2f5dae24382cc927c7a802a769a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761580
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 11:13:50 -07:00
Konsta Holtta
5c9bb32adb gpu: nvgpu: remove {map,unmap}_gmmu_pages() 
The GPU page tables are always mapped to the CPU now, so they don't need
the nvgpu_mem_{begin,end}() calls.

Change-Id: Ic48eeed3a6f002c78f89ef07922cddf835337de3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761579
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 11:13:46 -07:00
Konsta Holtta
d8833c6da3 gpu: nvgpu: remove unnecessary nvgpu_memset calls 
Some graphics context buffers are explicitly cleared to zero after
allocation. That's not necessary because the allocator gives
zero-initialized memory already, so remove the clears.

Change-Id: I8f9913605801e35082762e7743762d97f88e1d12
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761578
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 11:13:42 -07:00
Konsta Holtta
610dafa1e0 gpu: nvgpu: don't use alloc_flags for subctx header 
No need to use the flags variant with no flags.

Change-Id: I14effca4e7071e91230dd89c435843d128e022b1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761577
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 11:13:39 -07:00
Konsta Holtta
dd146d42fc gpu: nvgpu: don't mem_{begin,end}() for gr 
Now that GR buffers always have a kernel mapping, remove the unnecessary
calls to nvgpu_mem_begin() and nvgpu_mem_end() on these buffers:

- global ctx buffer mem in gr
- gr ctx mem in a tsg
- patch ctx mem in a gr ctx
- pm ctx mem in a gr ctx
- ctx_header mem in a channel (subctx header)

Change-Id: Id2a8ad108aef8db8b16dce5bae8003bbcd3b23e4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760599
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 11:13:35 -07:00
seshendra Gadagottu
2dda362e63 gpu: nvgpu: kconfig: remove GK20A_PERFMON config 
Removed de-funct GK20A_PERFMON config from Kconfig,
since code related to this functionality removed
long ago and DEVFREQ is getting used for gpu frequency
scaling.

Change-Id: Ic6828117a06f09446b64c789a1475c520ca520f8
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747883
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 11:13:32 -07:00
seshendra Gadagottu
8fe918c8d2 gpu: nvgpu: check for valid scaling profile data 
Check for valid scaling profile private data before making
calls to bandwidth manager.

Bug 200423741

Change-Id: Iff12b4a26ff0dfb2c32248b325a07e97f2de4e98
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1763601
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 10:04:12 -07:00
Thomas Fleury
2a9c4ce2cc gpu: nvgpu: gp106: fix scaling for mclk 
Change mclk scaling factor from 2 to 4, as we use dramdiv4 to
measure effective frequency.

Bug 2212598

Change-Id: I154a74712dbedf315f755ee51f75a06795841a1c
Reviewed-on: https://git-master.nvidia.com/r/1761896
(cherry picked from commit 35e26a5165ac08f783420343262e05e1d6d82996)
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762345
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 01:14:09 -07:00
Debarshi Dutta
1bc1ff2e92 gpu: nvgpu: remove use of struct fence type. 
struct fence and fence* APIs have changed to struct dma_fence
and dma_fence* respectively. This patch makes the required changes that
avoids using the struct fence type to prevent making API changes in nvgpu.

Bug 200417423

Change-Id: I566de58a3659cbc2495670136dc2fc65862b46e7
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1754164
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 00:25:29 -07:00
Debarshi Dutta
74d786dd13 gpu: nvgpu: disable powergating for kernel-4.14 in gp10b temporarily. 
All the powergating features such as railgating and other clock-gating
are disabled temporarily for kernel-4.14 which leads to several kernel-panics.
These will be re-enabled later.

Bug 200414723
Bug 200424473

Change-Id: I72b95bf027517309bd4ae32d0513e458ae46283f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756503
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-28 00:25:25 -07:00
Konsta Holtta
7998233b77 gpu: nvgpu: move submit code to common 
To finish OS unification of the submit path, move the
gk20a_submit_channel_gpfifo* functions to a file that's accessible also
outside Linux code.

Also change the prefix of the submit functions from gk20a_ to nvgpu_.

Jira NVGPU-705

Change-Id: I8ca355d1eb69771fb016c7a21fc7f102ca7967d7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760421
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-27 18:40:16 -07:00
Alex Waterman
2ac6fb4253 gpu: nvgpu: posix: Fix ffs() and fls() impl in POSIX 
The GCC builtins act slightly differently than the Linux versions
of these functions. This patch adds the necessary glue to emulate
the Linux versions identically.

JIRA NVGPU-525

Change-Id: Idadbecdfd516c68f3d3eb20eca495dc1eaa02c5b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1741951
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-27 08:42:52 -07:00
Deepak Goyal
0b0b820911 PMU: t19x: PMU ucode update. 
Remove Gr engine reset during ELPG entry.

Engine reset is causing clock gating logic to get reset thus
clock gating gets disabled during ELPG entry sequence.

It leads to higher power numbers observed at light graphics.
Removing GR reset during ELPG entry helped save power.

Bug 2180198

Change-Id: I957951eb93f9d044f4d9a908f2b56a4903dfbfad
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1757695
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-27 08:10:27 -07:00
Thomas Fleury
c60d8b7520 gpu: nvgpu: add bios debugfs node 
Add bios debugfs node to get current VBIOS version.

Bug 2113607

Change-Id: I8d52b651f923080000a4ad529e7efa05667563ba
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1743030
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-27 07:30:06 -07:00
Vaikundanathan S
ce5bd347aa gpu:nvgpu: Enable P-State for Gv100 
Bug 200399373

Change-Id: Ia5d7be7cdb5679c867350da515978d156984a6ea
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726914
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-26 22:23:26 -07:00
Alex Waterman
0b02c8589d Revert: GV11B runlist preemption patches 
This reverts commit 2d397e34a5.
This reverts commit cd6e821cf6.
This reverts commit 5cf1eb145f.
This reverts commit a8d6f31bde.
This reverts commit 067ddbc4e4.
This reverts commit 3eede64de0.
This reverts commit 1407133b7e.
This reverts commit 797dde3e32.

Looks like this makes the ap_compute test on embedded-qnx-hv
e3550-t194 quite bad. Might also affect ap_resmgr.

Signed-off-by: Alex Waterman <alexw@nvidia.com>
Change-Id: Ib9f06514d554d1a67993f0f2bd3d180147385e0a
Reviewed-on: https://git-master.nvidia.com/r/1761864
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2018-06-26 14:43:08 -07:00
Aparna Das
8586414cc1 gpu: nvgpu: fix perf output buffer size validation 
Currently we check if offset + size of perf output buffer crosses
4GB boundary. This check should be fixed to offset + size - 1.

Bug 200422626

Change-Id: I87b1c0761a97903780ddde871d5ca396bf26170d
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1758338
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-26 11:17:49 -07:00
Ashish Srivastava
10c3d4447d gpu: nvgpu: gv11b: enable RMW for gpu atomics 
Separate HAL added in gv11b and gv100 for
init_gpc_mmu function.
In gv11b HAL, RMW is enabled for gpu atomics
as default.
In gv100 HAL, GPC atomic capability mode will
get set based on the FB MMU capability.
If GPU is connected through NVLINK then mmu
will be set to RMW mode, else it will be in
L2 mode.

Bug 200390336

Change-Id: I224934f83d1762ec864ef8da7265dd01d86893a0
Signed-off-by: Ashish Srivastava <assrivastava@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1735137
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-26 11:17:17 -07:00
Alex Waterman
2d397e34a5 gpu: nvgpu: Remove variable that's only ever set 
Remove a variable that is only set but never used. Necessary
for userspace builds to compile.

JIRA NVGPU-525

Change-Id: Ie2f8f90e002a09f089a96a270c264ea1815445ad
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760666
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2018-06-25 12:10:13 -07:00
Alex Waterman
e1a6ab0b27 gpu: nvgpu: posix: Add missing bus C files to Makefile.sources 
Add two missing bus files to the userspace build. This caused
a couple of missing symbol problems when compiling.

JIRA NVGPU-525

Change-Id: I6566e35166b4b2b00a4e8960f0728bf59957d363
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1757490
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-25 12:04:38 -07:00
Alex Waterman
8569be52c2 gpu: nvgpu: posix: Define __user to nothing in POSIX 
This __user field is used to annotate certain varibles in Linux.
So define it in the POSIX headers so that common code can compile
even with these Linux annotations.

JIRA NVGPU-525

Change-Id: I417436ac40ed12f6551da600d8824f9bd7c191af
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1757489
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-25 12:04:35 -07:00
seshendra Gadagottu
a012527dbd gpu: nvgpu: gv11b: fix fb flush issue 
membar.sys does synchronization with the whole system (GPU and CPU),
membar.gl does synchronization within the GPU.
In gv11b, fb flush is generating membar.gl instead of membar.sys, which
is an issue. To fix this issue. following WAR is used:
1. Use bar1 engine id and bind it to a particular pdb,
2. Then instead of a fb_flush, issue a tlb invalidate of the bar1 pdb.

Now allocation of vm for bar1 instance block and bar1 binding is done
without check for bar1 support. Only bar1 register mapping is done
based on bar1 support enabled.

Bug 2112790

Change-Id: I76f43f1178a68f10823d48bc9da55d2bd686dd52
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1750257
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-25 10:54:56 -07:00
Seema Khowala
cd6e821cf6 gpu: nvgpu: gv11b: add runlist abort & remove bare channel 
-Add support for aborting runlist/s. Aborting runlist/s,
 will abort all active tsgs and associated active channels
 within these active tsgs
-Bare channels are no longer supported. Remove recovery
 support for bare channels. In case there are bare
 channels, recovery will trigger runlist abort

Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596

Change-Id: I6bec8a0004508cf65ea128bf641a26bf4c2f236d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640567
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-24 09:53:44 -07:00
Seema Khowala
5cf1eb145f gpu: nvgpu: gv11b: preempt runlist if tsg preempt times out 
-Even though tsg preempt timed out, teardown sequence would by
 design require s/w to issue another preempt.
 If recovery includes an ENGINE_RESET, to not have race conditions,
 use RUNLIST_PREEMPT to kick all work off, and cancel any context
 load which may be pending. This is also needed to make sure
 that all PBDMAs serving the engine are not loaded when engine is
 reset
-Add max retries for pre-si platforms for runlist preempt done
 polling loop

Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596

Change-Id: If9d1731fc17e7e7281b24a696ea0917cd269498c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709902
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-24 09:53:40 -07:00
Seema Khowala
a8d6f31bde gpu: nvgpu: gv11b: acquire/release runlist_lock during teardown 
Recovery can be called for various types of faults. Make
sure current teardown is done before proceeding to next one.

Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596

Change-Id: I2073cc4f659fcc2103cb1fc8b7d9e1b2f1fb466f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1662681
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-24 09:53:36 -07:00
Seema Khowala
067ddbc4e4 gpu: nvgpu: remove timeout_rc_type i/p param 
-is_preempt_pending hal does not need timeout_rc_type input param as
 for volta, reset_eng_bitmask is saved if preempt times out. For
 legacy chips, recovery triggers mmu fault and mmu fault handler
 takes care of resetting engines.
-For volta, no special input param needed to differentiate between
 preempt polling during normal scenario and preempt polling during
 recovery. Recovery path uses preempt_ch_tsg hal to issue preempt.
 This hal does not issue recovery if preempt times out.

Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596

Change-Id: Ie76a18ae0be880cfbeee615859a08179fb974fa8
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709799
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-24 09:53:33 -07:00
Seema Khowala
3eede64de0 gpu: nvgpu: gv11b: preempt timeout set to 1000 ms 
For Si platforms, gk20a_get_gr_idle_timeout returns
3000 ms i.e. 3 sec. Currently this time is used for
polling each pbdma, eng and runlist and this conflicts
channel timeout if preempt fails.
Use 1000 ms timeout for polling preempt timeout when
timeouts are enabled else use gk20a_get_gr_idle_timeout.
For non-si platforms, polling loop is depending on
max number of retries.

Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596

Change-Id: Icdb69b7b7d17292f2b6a43f1d8e9d75ff545d0ae
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1739543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-24 09:53:23 -07:00
Seema Khowala
1407133b7e gpu: nvgpu: gv11b: do not poll preempt done if eng intr pending 
-During polling eng preempt done, reset eng only if eng stall
 intr is pending. Also stop polling for eng preempt done
 if eng intr is pending.
-Add max retries for pre-si platforms for poll pbdma and eng
 preempt done polling loops.

Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596

Change-Id: I66b07be9647f141bd03801f83e3cda797e88272f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694137
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-24 09:53:20 -07:00
Seema Khowala
797dde3e32 gpu: nvgpu: gv11b: disable/enable runlist sched during tsg preempt 
Disable sched before tsg preempt and re-enable after preempt
is done or timed out. This is a WAR to fix Bug 2065990.

Bug 2065990

Change-Id: I5f807449960d83366a3ed8c352ba4627fc1e7836
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665319
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-24 09:53:11 -07:00
Vaibhav Kachore
f37d958ce2 gpu: nvgpu: gv100: add support for FECS trace 
- This patch sets required fecs trace functions to hals.
- In gv100, GPU VA needs to programmed in ucode to
get FECS trace. Hence, setting this "NVGPU_FECS_TRACE_VA"
characteristic to be true.

EVLR-2708

Change-Id: I41845a1db8452b8e3fa9d67ecc4cabfac503fd0b
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747269
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-22 16:12:14 -07:00
Terje Bergstrom
8351b54160 gpu: nvgpu: Use nvgpu_alloc_vid_at for dGPU ACR 
ACR allocates buffers from vidmem and passes explicitly flag
NVGPU_DMA_NO_KERNEL_MAPPING. Vidmem buffers are never mapped to CPU,
and dGPU ACR does not actually care, so switch to using
nvgpu_alloc_vid_at(). This removes another explicit dependency
to NVGPU_DMA_NO_KERNEL_MAPPING, which is going to be removed.

Change-Id: I532d40c5ba9e71f07461c526bd2a43e1eb01a290
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1753711
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-22 10:04:30 -07:00
Terje Bergstrom
f2f03582fd gpu: nvgpu: Add nvgpu_dma_alloc_vid_at() 
Add a wrapper function nvgpu_dma_alloc_vid_at() for performing vidmem
allocation at a specific address without needing to pass any flags.

Change-Id: Ib7a21a4fd33120749cf7b79750c3a382ba08b470
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1753710
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-22 10:04:26 -07:00
Alex Waterman
840e039d57 gpu: nvgpu: Update Linux side VM code for API solidification 
Update the Linux specific code to match the MM API docs in the
previous patch. The user passed page size is plumbed through
the Linux VM mapping calls but is ultimately ignored once the
core VM code is called. This will be handled in the next
patch.

This also adds some code to make the CDE page size picking
happen semi-intelligently. In many cases the CDE buffers can
be mapped with large pages.

Bug 2011640

Change-Id: I20e78e7d5a841e410864b474179e71da1c2482f4
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1740610
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-22 10:04:16 -07:00
Alex Waterman
a6e3403f46 gpu: nvgpu: Update __get_pte_size() to check IOMMU-ability 
When generating the PTE size for a given mapping the code must
consider whether the GPU is being IOMMU'ed. The presence and
usage of an IOMMU implies the buffers will appear contiguous
to the GPU. Without an IOMMU we cannot assume that and therefor
must use small pages regardless of the size of the buffer to
be mapped.

Bug 2011640

Change-Id: I6c64cbcd8844a7ed855116754b795d949a3003af
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1697891
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-22 10:03:55 -07:00
Debarshi Dutta
2bc421dd52 gpu: nvgpu: resolve missing -ENOSYS error 
Added the header #include <nvgpu/errno.h> in os_fence.h

Bug 200414723

Change-Id: I2a4290d2b9f80fdb66665ff4c8e8f3f163b9f2c3
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-21 23:43:18 -07:00
Debarshi Dutta
d2f41c8746 gpu: nvgpu: resolve missing kfree error message 
Insert the header <linux/slab.h> to resolve the kfree error for driver_common.c

Bug 200414723

Change-Id: I2696b88d3a29decb2c984f69295274ccda6c0069
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721522
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-21 23:43:14 -07:00
Debarshi Dutta
fbf84dc2e3 gpu: nvgpu: resolve missing DMA_ERROR_CODE error message. 
Add the header <linux/dma-mapping.h> to nvgpu_mem.c file to
resolve compilation errors in linux-4.14

Bug 200414723

Change-Id: Ie6fd532688a1bf6d9705d423fcfde660693a3654
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721526
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-21 23:43:10 -07:00
Konsta Holtta
939d3d5c4c gpu: nvgpu: zero prealloc indices on init 
Initialize the prealloc job list put and get indices to zero when
allocating these resources. Otherwise we'd get whatever got left from
the channel's previous lifetime.

Change-Id: Idb17ec7bfbd0c1e2121c7a63e41dc5845560e988
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756871
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-06-21 13:58:10 -07:00