Commit Graph

9 Commits

Author SHA1 Message Date
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-06 02:56:53 -07:00
Deepak Nibade
4ba9592877 gpu: nvgpu: add common.gr.setup api to free subctx
Add new API nvgpu_gr_setup_free_subctx() in common.gr.ctx to free subctx
Call this via hal g->ops.gr.setup.free_subctx()

Subctx allocations happens through gr.setup api right now hence it makes
sense to provide subctx free api through same unit

Remove g->ops.channel.free_ctx_header() hal since we now have gr.setup
hal

Remove gv11b/subctx_gv11b.* files since they are no longer needed and
all the code in them has been moved to common units

Jira NVGPU-1886

Change-Id: I3d58fc3665ed9b6ffba830249a4cd30af7b857f4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094994
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-04-14 17:33:54 -07:00
Seema Khowala
b4ec1c5dff gpu: nvgpu: move dump_channel_status from fifo to channel
Renamed and moved from fifo to channel
gk20a_debug_dump_all_channel_status_ramfc -> nvgpu_channel_debug_dump_all
gk20a_dump_channel_status_ramfc -> gk20a_channel_debug_dump
gv11b_dump_channel_status_ramfc -> gv11b_channel_debug_dump

Moved nvgpu_channel_dump_info struct to channel.h
Moved nvgpu_channel_hw_state struct to channel.h
Moved dump_channel_status_ramfc fifo ops to channel ops
as debug_dump

JIRA NVGPU-2978

Change-Id: I696e5029d9e6ca4dc3516651b4d4f5230fe8b0b0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092709
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2019-04-10 16:15:50 -07:00
Debarshi Dutta
eaab8ad1f2 gpu: nvgpu: move some fifo based HAL ops to hal.channel unit
a) free_channel_ctx_header is used to free the channel's underlying subctx
and belongs to the hal.channel unit instead of fifo. Moved the same and
renamed the HAL ops to free_ctx_header. The function
gv11b_free_subctx_header is moved to channel_gv11b.* files and also
renamed to gv11b_channel_free_subctx_header.

b) ch_abort_clean_up is moved to hal.channel unit

c) channel_resume and channel_suspend are used to resume and suspend all
the serviceable channels. This belongs to hal.channel unit and are
moved from the hal.fifo unit.

The HAL ops channel_resume and channel_suspend are renamed to
resume_all_serviceable_ch and suspend_all_serviceable_ch respectively.

gk20a_channel_resume and gk20a_channel_suspend are also renamed to
nvgpu_channel_resume_all_serviceable_ch and
nvgpu_channel_suspend_all_serviceable_ch respectively.

d) set_error_notifier HAL ops belongs to hal.channel and is moved
accordingly.

Jira NVGPU-2978

Change-Id: Icb52245cacba3004e2fd32519029a1acff60c23c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083593
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-09 01:48:16 -07:00
Philip Elcan
c0b65e8b05 gpu: nvgpu: fifo: fix MISRA 10.3 violations
MISRA Rule 10.3 prohibits assigning objects of different essential or
narrower type. This fixes MISRA 10.3 violations in the common/fifo unit.

JIRA NVGPU-3023

Change-Id: Ibab6704e8d3cffd37c6c0e31ba6fc6c0bb7b517b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087812
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2019-04-08 19:54:00 -07:00
Konsta Holtta
38c548a39c gpu: nvgpu: Add channel.reset_faulted HAL
Add a HAL op for resetting the eng_faulted and pbdma_faulted states on a
channel. This used to be a local feature in fifo_gv11b.c; the HAL is
defined for all chips from gv11b onwards.

Jira NVGPU-1307

Change-Id: I120a59c429851cc69e712ddd5b06a4b3d16c06c9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017269
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-02-12 17:06:37 -08:00
Konsta Holtta
9457a5ea91 gpu: nvgpu: add eng_faulted to channel HAL for gv11b+
The ccsr_channel_eng_faulted field exists from Volta onwards. Implement
the read_state HAL op for those chips, and store that bit as a boolean
in the channel state info.

Jira NVGPU-1307

Change-Id: Ie997892f2d3db0725496661a4d3083e7396894cc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017267
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-12 17:06:18 -08:00
Konsta Holtta
7189630e7c gpu: nvgpu: drop fifo_ in channel HAL names
Now that the moved HAL ops from fifo are in channel, rename the
implementations to match.

Jira NVGPU-1307

Change-Id: I7b9336f506c9e71bcd0af98886216958bd6695eb
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017264
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2019-02-12 17:05:56 -08:00
Konsta Holtta
5cde4c2140 gpu: nvgpu: move chip specific channel reg ops to common
Extract out the HAL ops' implementation that now belongs to the channel
unit. This unit is responsible for channel register accesses and the
like (ccsr_*).

Rename channel_gm20b_bind to gm20b_fifo_channel_bind to match with the
rest of the naming. Same with channel_gv11b_unbind.

Jira NVGPU-1307

Change-Id: I58b9d96dbdaf36bdb163a5729544a41faec828ab
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017262
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-12 17:05:43 -08:00