Commit Graph

11 Commits

Author SHA1 Message Date
Seema Khowala
6ba1f5db3b gpu: nvgpu: move chip specific teardown_mask/unmask_intr
Move chip specific functions for teardown_mask_intr and
teardown_unmask_intr to hal/fifo/fifo_intr_[chip].[ch]

Renamed
teardown_mask_intr -> intr_set_recover_mask
teardown_unmask_intr -> intr_unset_recover_mask

JIRA NVGPU-1314

Change-Id: If233565cbdb09d77cfebd4346edcc3fe64584355
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093980
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2019-04-18 15:55:53 -07:00
Seema Khowala
c570ba99ed gpu: nvgpu: move sched error bad tsg recovery
Move sched error bad tsg recovery from fifo_intr_gv11b.c
to common/rc/rc.c

JIRA NVGPU-1314

Change-Id: Ic731a3162cad2fe184d764f0b3ad98acc1f382cb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095621
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-04-16 17:05:49 -07:00
Seema Khowala
1882a7413d gpu: nvgpu: move runlist update timeout rc to common/rc
Move runlist update timeout recovery from runlist.c to
rc.c
Move RC_TYPE defines from fifo.h to rc.h

JIRA NVGPU-1314

Change-Id: I66925ca9fba904c523be69ad99808e3de33a7d46
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093666
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2019-04-16 17:05:10 -07:00
Rajesh Devaraj
5fd2175509 gpu: nvgpu: Enable the reporting of PFIFO errors
- Enable the reporting of PFIFO related errors such as engine syncpoint error,
  memop timeout error, lb error to 3LSS framework.
- Remove the reporting of bind_error from gk20a since we already report it
  from gv11b related fifo hal file.

Jira NVGPU-3087

Change-Id: Ic002be3a12a049010165870b861cdfb13a7f33d8
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088579
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2019-04-07 22:44:06 -07:00
Debarshi Dutta
52cbc88a00 gpu: nvgpu: add pbdma intr_enable HAL ops.
A new HAL ops intr_enable() is constructed in
hal.fifo.pbdma unit. The implementation for this HAL ops
is based on gm20b and gv11b architectures.

Jira NVGPU-2950

Change-Id: Ifd9c3bfad4264449c52f411e8cad8674c3756048
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073536
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2019-03-28 01:15:07 -07:00
Debarshi Dutta
ce5c43d24a gpu: nvgpu: re-org top level pbdma interrupt handler
fifo_pbdma_isr is moved to fifo_intr_gk20a HAL unit and renamed to
gk20a_fifo_pbdma_isr.

The pbdma specific handling part of the function
gk20a_fifo_handle_pbdma_intr is now separated into a top level HAL
function named handle_pbdma_intr. This HAL function is implemented
for GM20B and all the other architectures use the same implementation.
handle_pbdma_intr can accept NULL values for the parameters handled and
error_notifier.

gk20a_fifo_handle_pbdma_intr is called from
gv11b_fifo_poll_pbdma_chan_status and gk20a_fifo_pbdma_isr.
The call to gk20a_fifo_handle_pbdma_intr from
gv11b_fifo_poll_pbdma_chan_status doesn't progress to recovery.
Thus, the function gk20a_fifo_handle_pbdma_intr is removed to decouple
pbdma handling from recovery. gv11b_fifo_poll_pbdma_chan_status now
directly calls the HAL handle_pbdma_intr. For gk20a_fifo_pbdma_isr,
rc_type is used to proceed to recovery by calling
gk20a_fifo_pbdma_fault_rc.

gk20a_fifo_pbdma_fault_rc is changed to public from static.

Jira NVGPU-2950

Change-Id: I4f3597aca2317d4b745cd47bab9dd95c927160a9
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073535
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2019-03-28 01:14:53 -07:00
Seema Khowala
dfafddcc21 gpu: nvgpu: move common and chip specific ctxsw timeout
Delete apply_ctxsw_timeout_intr ops and add
ctxsw_timeout_enable ops

Move chip specific sched_error and ctxsw_timeout
functions to hal/fifo/fifo_intr_* and hal/fifo/ctxsw_timeout_*

Add nvgpu_rc_ctxsw_timeout function under common/rc/rc.c

Do not check ctxsw timeout for channels that are no more
bound to tsg.

JIRA NVGPU-1312

Change-Id: Ide977fb60b3b72a27d9f22873f7a416c3bd1181d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075734
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2019-03-25 22:47:45 -07:00
Seema Khowala
c809831da5 gpu: nvgpu: move ch and tsg specific ctxsw timeout
Move check_ch_ctxsw_timeout under channel ops as
check_ctxsw_timeout

Move check_tsg_ctxsw_timeout under tsg ops as
check_ctxsw_timeout

JIRA NVGPU-1312

Change-Id: If1711769176e4ee5945a00a61eab7bd67f6f665d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076826
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2019-03-25 22:47:26 -07:00
Seema Khowala
fe2a599700 gpu: nvgpu: rename fifo_eng_timeout_us
Rename fifo_eng_timeout_us to ctxsw_timeout_period_ms for
clarity.

JIRA NVGPU-1312

Change-Id: I23faff3df7160c1193f797ac03769ef2ecf4449e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076776
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2019-03-25 22:47:09 -07:00
Seema Khowala
9393e2a90a gpu: nvgpu: rename timeout of channel struct to wdt
Rename channel_gk20a_timeout to nvgpu_channel_wdt.
Rename timeout variable of channel_gk20a struct to wdt.
Rename ch_wdt_timeout_ms to ch_wdt_init_limit_ms.

Rename gk20a_channel_timeout_* to nvgpu_channel_wdt_*

JIRA NVGPU-1312

Change-Id: Ida78426cc007b53f3d407cf85428d15f7fe7518a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077641
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2019-03-25 22:46:52 -07:00
Seema Khowala
f66f3e1341 gpu: nvgpu: move fifo intr to hal/fifo
Removed intr_0_error_mask ops

Added below ops for fifo intr
intr_0_enable
intr_1_enable
intr_0_isr
intr_1_isr

JIRA NVGPU-1310

Change-Id: I19bd1a380a89cffd582d6c4a0b7796a46fec5afb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072144
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2019-03-25 11:03:39 -07:00