Previously initializing buddy_allocator with size=0 initialized large
memory block. With fixes in buddy_allocator_init() function, size = 0
triggered segmentation fault and so size was temporarily updated to
fixed value.
This patch updates buddy_allocator_init() function to return error if
requested size of buddy_allocator is zero. As kernel VMA is absent for
VGPU, this patch also updates nvgpu_vm_do_init() function to not
allocate kernel VMA with size = 0.
Jira NVGPU-3005
Change-Id: I568fbbff6ac2c66395d1dc5a4b35304c7f4002fb
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113190
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 5.7 doesn't allow reuse of tag or variable names as this
would lead to developer confusion. Patch renames page_alloc_slab_page
struct pointer's local variable name to page_ptr to resolve the
violation. Also, renames function "nvgpu_page_alloc" to
"nvgpu_page_balloc" to remove identifier name overloading.
MISRA rule 10.x forbids from casting value of composite expression to an
object with different essential type category. This patch replaces
multiplication operation to left shift operation.
MISRA rule 15.7 requires every if .. else if construct to be terminated
with an else statement. This patch updates if .. else if condition to
resolve the violation.
MISRA Rule 17.2 doesn't allow recursive call from a function to itself,
as this might lead to stack overflow. Updated nvgpu_page_allocator_init
to call nvgpu_buddy_allocator_init() directly.
MISRA rule 21.6 doesn't allow use of snprintf from standard library.
This patch replaces snprintf call with string functions.
JIRA NVGPU-3338
Change-Id: Ic8cb956edb3c72811752008de192e6e8ba12463e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.
Jira NVGPU-3248
Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 17.2 prohibits indirect recursion. nvgpu_allocator_initi()
was calling nvgpu_page_allocator_init(), which in turn was calling back
to nvgpu_allocator_init() to init a buddy allocator. Rather than
calling back to nvgpu_allocator_init(), have nvgpu_page_allocator_init()
call nvgpu_buddy_allocator_init() directly.
JIRA NVGPU-3332
Change-Id: I1102450ae26dda355d5f5dcc3ddb195871c26c32
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114028
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This fixes MISRA rule 4.7 violations in the function nvgpu_vm_map(). The
violations were caused by trying to use ERR_PTR() to return error
information. Rather than try to return errors in a pointer, just change
the API to return an int and pass the pointer the arguments.
JIRA NVGPU-3332
Change-Id: I2852a6de808d9203b8c7826e2b8211bab97ccd16
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Fix Rule 4.7 violation for failing to check return value.
Fix Rule 14.2 violation when using the nvgpu_list_for_each_entry_safe
macro by refactoring to use a while loop.
Fix Rule 13.5 violation for using a nvgpu_timeout_expired_msg() in a
logical expression because it can have side effects. This was fixed by
refactoring the while loop.
JIRA NVGPU-3332
Change-Id: I1454db82f766a06d3ffd549de43aad6e1b632928
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114026
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Below MISRA 10.4 violation is reported in nvgpu.common.mm.vm_area
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/vm_area.c:234:
misra_violation: The condition clause expression of the for loop has
persistent side-effects.
Fix this by replacing with a while loop.
Jira NVGPU-3330
Change-Id: Ica6882d6c73dc0d74159f34279d8f91b7494c65c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117059
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 21.6 violation is reported in nvgpu.common.mm.as
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:79:
misra_violation: Using function "snprintf".
Fix this by replacing snprintf with strncpy.
Add nvgpu_strnadd_u32 function to convert u32 to string
The function supports radix from 2 to 16.
Jira NVGPU-3333
Change-Id: Idee739dfdedeabb74d0d9f7d4cddd798445f0ee1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117019
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Below MISRA 10.4 violation is reported in nvgpu.common.mm.nvgpu_sgt
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/nvgpu_sgt.c:131:
misra_violation: Essential type of the left hand operand
"mem->mem_flags & 8ULL" (unsigned) is not the same as that of the
right operand "0ULL"(signed).
Fix this by changing right hand operand to 0U.
Jira NVGPU-3334
Change-Id: Ib28bfce363a807ba9f8fa9df9cbb02c636a74898
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117034
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 17.7 violation is reported in nvgpu.common.mm.mm
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:645:
misra_c_2012_rule_17_7: The return value of a non-void function
"*g->ops.bus.bar1_bind" is unused.
Fix this by checking return value and returning an error in
case of failure.
Jira NVGPU-3331
Change-Id: Iab43d630163af782d3cc87989a64062516a4cd92
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116706
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.1 violation is reported in nvgpu.common.mm.mm
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:378:
misra_violation: The expression "g->mm.vidmem.size" of non-boolean
essential type is being interpreted as a boolean value for the
operator "&&".
Fix this by explicitly checking g->mm.vidmem.size > 0U.
Jira NVGPU-3331
Change-Id: I1bb54736593801c7cb684973f411459dae6f008d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116705
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule 11.2 doesn't allow conversion to or from an incomplete type
pointer, as it may result incorrect point alignment and may further lead
to undefined behavior.
MISRA Rule 16.x requires all switch statements to be well-formed with
terminating break statement for every switch-clause.
This patch fixes 11.2 and 16.x violations in common.mm.nvgpu_mem.
Jira NVGPU-3339
Change-Id: I002393cc64d44826e6954d1bf6af71bd569e862f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113096
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 21.3 forbids from using calloc, malloc, realloc and free
identifiers for function or macro names. This patch renames nvgpu
allocator free operator to free_alloc to follow rule 21.3.
Jira NVGPU-3336
Change-Id: Ie9f48d567255a3e1dca70632fbe3d36b45023f3f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move the gv11b MMU fault handling code into a new mm.mmu_fault HAL.
Also move the existing gmmu_mmu_fault HAL code into this HAL as they
are basically the same logical entity.
JIRA NVGPU-2042
JIRA NVGPU-1313
Change-Id: I41d3e180c762f191d4de3237e9052bdc456f9e4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109693
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Currently, bitmap allocator reuses identifier "nvgpu_bitmap_alloc" for
an allocation function and as bitmap rbtree node struct. Renaming the
allocation function to "nvgpu_bitmap_balloc". Also, renaming fixed
allocation function to "nvgpu_bitmap_balloc_fixed" for consistency.
Jira NVGPU-3335
Change-Id: I6fe616db5137b2d4e2795a84ae5eafd527f0dba5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110714
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 2.2 defines dead code as "operations which are executed but
removal of these operations has no effect on program behavior".
Variable initializations violate this rule if initialized value is not
used and replaced.
This patch fixes some of these reported violations.
Jira NVGPU-858
Change-Id: I694517ace8884c78c63f6346e455078d19b70b4d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110459
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.
Much of this is fairly straightforward copy/paste and updates to the
HAL init files.
The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.
JIRA NVGPU-2042
Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The alloc_insty_block() function in the MM HAL is not a HAL. It does
not abstract any HW accesses; instead it just wraps a dma allocation.
As such remove it from the HAL and move the single gk20a implementation
to common/mm/mm.c as nvgpu_alloc_inst_block().
JIRA NVGPU-2042
Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109049
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move the gk20a_init_mm_setup_hw to common code. This function just
calls HALs to initialize various bits of HW. However, since this
code assumes that (some of) the HALs are present this code is treated
as a vGPU HAL (that is it's NULL for vGPU).
This patch also renames the MM HW init HAL.
Sicne the gv11b variant of this setup_hw HAL did have some differences
from the gk20a version the new common version required some work. The
gv11b code was copied into the common function but now the gv11b
specific calls were HAL'ified (since they will need to be anyway for
the MMU fault buf code) and protected by an if-condition.
JIRA NVGPU-2042
Change-Id: I959293394ee8793923d858ee37b7ce346096654f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104541
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This "HAL" exists to handle the vGPU specific bind channel operation.
This patch moves the native function implementation to common/mm/vm.c
and renames the gk20a to nvgpu to follow the convention for vGPU vs
native HAL functions.
JIRA NVGPU-2042
Change-Id: I02b9ebf0d53d58a6d2ede544e34f2b8ff1b1eb42
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104540
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Currently, buddy, page and bitmap allocators have individual init()
functions. This patch creates common nvgpu_alloc_allocator_init()
function to trigger the individual functions based on allocator type
argument. This makes writing requirements for the allocators easier.
Jira NVGPU-991
Change-Id: If94e3496f46f036460ef9f1831852e6fc19d3a0b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2097962
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Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.
This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.
JIRA NVGPU-2042
Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099693
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Rename the two native GPU GMMU map/unmap functions and update the
HAL initializations to reflect this:
gk20a_locked_gmmu_map -> nvgpu_gmmu_map_locked
gk20a_locked_gmmu_unmap -> nvgpu_gmmu_unmap_locked
This matches what other units do for handling vGPU "HAL" indirection.
Also move the function declarations to <nvgpu/gmmu.h> since these are
shared among all non-vGPU chips. But since these are still technically
HAL operations they should never be called directly. This is a bit of
an organixational issue that I have not thought through hwo to solve
yet.
Ideally they would go into a "hal/mm/gmmu/" include somewhere, but
that A) doesn't yet exist, and B) those are chip specific; these
functions are native specific. Ugh.
JIRA NVGPU-2042
Change-Id: Ibc614f2928630d12eafcec6ce73019628b44ad94
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099692
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add a new MM HAL directory to contain all MM related HAL units.
As part of this change add cache unit to the MM HAL. This contains
several related fixes:
1. Move the cache code in gk20a/mm_gk20a.c and gv11b/mm_gv11b.c to
the new cache HAL. Update makefiles and header includes to take
this into account. Also rename gk20a_{read,write}l() to their
nvgpu_ variants.
2. Update the MM gops: move the cache related functions to the new
cache HAL and update all calls to this HAL to reflect the new
name.
3. Update some direct calls to gk20a MM cache ops to pass through
the HAL instead.
4. Update the unit tests for various MM related things to use the
new MM HAL locations.
This change accomplishes two architecture design goals. Firstly it
removes a multiple HW include from mm_gk20a.c (the flush HW header).
Secondly it moves code from the gk20a/ and gv11b/ directories into
more proper locations under hal/.
JIRA NVGPU-2042
Change-Id: I91e4bdca4341be4dbb46fabd72622b917769f4a6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095749
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Moved fb interrupt handling related code to fb intr sub-unit.
Moved following hals from fb hal to fb intr hal and renamed to:
void (*enable)(struct gk20a *g);
void (*disable)(struct gk20a *g);
void (*isr)(struct gk20a *g);
gk20a_readl/writel are replaced with nvgpu_read/writel.
Hals are populated with new function names and code is modified
to call new hals.
Moved ecc interrupt to gv11b_fb_intr_handle_ecc in a separate file:
fb_intr_ecc_gv11b.c/h
JIRA NVGPU-2034
Change-Id: I80c7110c902c4e082561cf7cbe65c20eb9acb661
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090070
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Bugs in current version are listed below:
1. Function alloc() or alloc_pte() allocate memory for len=0.
2. Function alloc() or alloc_pte() don't unlock nvgpu_allocator if
pte_size is invalid.
3. Function alloc_pte() and alloc_fixed() set alloc_made flag
unconditionally.
4. Function release_carveout() tries to acquire nvgpu_allocator lock
twice causing unresponsive state.
5. If buddy allocation fails in balloc_do_alloc() or
balloc_do_alloc_fixed() function, previously allocated buddies are not
merged. This causes seg fault in ops->fini().
6. With gva_space enabled and base=0, buddy_allocator updated base not
checked for pde alignment.
7. In balloc_do_alloc_fixed(), align_order computed using __fls()
results in one order higher than requested.
8. Initializing buddy allocator with size=0, initializes very large
memory and will trigger seg fault with the changes in this patch.
Setting size=1G so that further execution is successful.
This patch fixes above listed bugs and updates following:
1. With gva_space enabled, BALLOC_PTE_SIZE_ANY is considered as
BALLOC_PTE_SIZE_SMALL which allows alloc() to be used.
2. GPU_BALLOC_MAX_ORDER changed to 63U. Condition added to check that
max_order is never greater than GPU_BALLOC_MAX_ORDER.
3. BUG() changed to nvgpu_do_assert().
JIRA NVGPU-3005
Change-Id: I20c28e20aa3404976d67f7884b4f8cbd5c908ba7
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075646
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Added the following HALs
- ramin.base_shift
- ramin.alloc_base
Use above HALs in mm, instead of using hw definitions.
Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits
Added missing #include for <nvgpu/mm.h>
Jira NVGPU-3015
Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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