-Message header is added as part of FB message queue to have
sequence number & checksum to perform sanity check on
received message.
-Made required changes in structs to read message correctly
from data member offset but skipped to handle sanity checks
in code as NvGPU not needed for current supported messages .
-Added support to handle cmd/msg queue element changes.
JIRA NVGPU-3724
Change-Id: I85dccfab8902cbf71752582666931f482c3ec408
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155165
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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
used.
Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.
Also, change users of ALIGN to pass unsigned types only.
JIRA NVGPU-3515
Jira NVGPU-3411
Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
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Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset. OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.
Jira NVGPU-3545
Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
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Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.
This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.
Jira NVGPU-3476
Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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pmu_ipc.c had functionality for rpc response handling and message cond
checks. This patch moves them to msg unit. And prepare cmd.h to group
together structs and functions related PMU commands.
JIRA NVGPU-1970
Change-Id: Iec5d72d02ab3ee51963631c828b301c56af8dc48
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079146
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queue specific sources should use general logging interfaces like
nvgpu_err, nvgpu_log_info and not PMU specific nvgpu_pmu_dbg. With
this we can remove pmu.h inclusion in engine_mem_queue.c and
engine_fb_queue.c. This uncovers some new header inclusions
that we have to do for compilation of both these files.
More cleanup of PMU fields and related headers to follow.
JIRA NVGPU-1994
Change-Id: I728746094de85f338fcae940f10ee1731d397048
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019415
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Some of the engine queue related defines are shared by PMU, SEC2 and
queue implementations and currently in gpmuif_cmn.h. Let us add
engine_queue.h header file to club all those defines together.
JIRA NVGPU-1994
Change-Id: I57a889e6d14d954d2660e513994bb87cbb1e5824
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019414
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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With engine queues implementations now isolated from falcon unit let us
move it to common with following units in the sources:
1. nvgpu.common.engine_queues.mem_queues.mem_queue
2. nvgpu.common.engine_queues.mem_queues.emem_queue
3. nvgpu.common.engine_queues.mem_queues.dmem_queue
4. nvgpu.common.engine_queues.fb_queue
5. nvgpu.common.falcon.falcon
6. nvgpu.common.hal.falcon
File/folder names are prepended with "engine_" for better understanding.
JIRA NVGPU-1994
Change-Id: I02b06f134e964b0ec665208ae4e08ae65504ed4e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016291
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