LSF loader cleanup, on gm20b/gp10b PMU falcon & other GR falcons
uses different struct to store loader config which needs different
functions to fill LSF loader config data, but on gv11b/gv10x/tu10a
uses common falcon struct to store loader config, so made single
function to fill LSF loader config data using ACR LSF struct &
removed duplicate code.
Removed ACR LSF loader ops which were part of PMU ops
to cleanup dependency
JIRA NVGPU-1148
Change-Id: I681829e05463d2517a4049433d8b0de3adeb06d9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012853
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Added data struct under ACR struct to manage LS falcons ucode
as LS falcon ucode holds multiple properties & can be set at acr
init stage to bootstrap LS falcons as required, at present LS falcons
code is part ACR & partially part of PMU code to setup LSF bootstrap,
so, needed to clean up the dependency.
JIRA NVGPU-1148
Change-Id: Ie206e129e3db838041db44d5227ab76a1de991c8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012763
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes pmu_payload_extract to return a status based
on the result of nvgpu_falcon_copy_from_dmem and propagates it upstream.
It also removes the pmu_payload_extract_rpc which appeared useless.
JIRA NVGPU-677
Change-Id: I299c500a356816f884abd1dc843ed18a37974cde
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008895
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes pmu_elpg_statistics to return a status based
on the result of nvgpu_falcon_copy_from_dmem and propagate it upstream.
JIRA NVGPU-677
Change-Id: I7c85bf2b1b9f5a8eb09040229a1112c84713eb70
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes a call to falcon_copy_from_dmem to handle
error codes.
JIRA NVGPU-677
Change-Id: Id0bb2b67aa0661e65880fe41d4cfd344dd362c32
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008815
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes calls to nvgpu_falcon_bootstrap to handle
error codes.
JIRA NVGPU-677
Change-Id: I1d9df6053c727e7eb3d99682ff7bb06267608a54
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008797
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common/pmu/pmu.c uses IS_ENABLED() to check if perfmon sampling
should be enabled. The flag it is checking was already removed, so
the condition always evaluates to false. Remove the reference to the
removed build flag. Perfmon sampling can now be enabled only via
debugfs.
Remove the definition of IS_ENABLED() in include/nvgpu/posix/types.h.
Change-Id: I26ddd9d24c39513db68c7ae2b1cd1ebdd980e96e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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pstate s/w setup needs to know offsets of boardobjs present
in PMU super surface to construct boardobj set/get_status
construct.
With SSMD support, boardobj offset will be part of SSMD
lookup table which is part of PMU super surface buffer &
updated by PMU RTOS during init stage.
As SSMD is updated at init stage & SSMD will be ready for nvgpu
to read offsets only when PMU init message is received,
so pstate s/w must wait till PMU is ready to construct
boardobj set/get_status
JIRA NVGPU-1874
Change-Id: I87d840965b92c538f26dbedf458f0c18d1808abc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000863
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Currently there are multiple BOARDOBJGRP SET/GET_STATUS construct
added to support for 3.5 pstate, _pack boardobjs & to fetch respective
offset/size of boardobjs from PMU super surface.
With super surface member descriptor(SSMD) support, boardobj offset
will be part of SSMD lookup table which is part of PMU super surface
buffer & updated by PMU RTOS during init stage,
So, making changes to use common BOARDOBJGRP SET/GET_STATUS
construct define which fetchs offset/size from SSMD,
& deleting other BOARDOBJGRP construct defines.
JIRA NVGPU-1874
Change-Id: I4e3d9ad31da33a836c5e9219321c68d867c2a172
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000860
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-SSMD - super surface member descriptor
-created new file pmu_super_sruface.c for super surface
related functions.
-Modified macros BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT and
BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT to fetch
offset/size using super surface related functions
-Moved functions nvgpu_pmu_super_surface_alloc() &
nvgpu_pmu_surface_free from pmu.c to pmu_super_sruface.c
-Created ops create_ssmd_lookup_table under pmu
to support function for chip specific
Currently, NVGPU must modify RM/PMU defined common super surface
data struct to match offset as per NVGPU super surface data struct
as NVGPU cannot include directly RM/PMU defined struct due to number
boardobjs supported by NVGPU, this adds extra work when there is
changes in boardobj or when need add support for new boardobj.
SO, to fix this issue SSMD feature is introduced.
With SSMD support, NVGPU required boardobjs offset will be part of
SSMD lookup table which is part of PMU super surface buffer & is
always first member of PMU super surface data struct for easy access,
SSMD lookup table will be copied to PMU super surface SSMD offset by
PMU RTOS ucode at init stage as per predefined SSMD lookup table.
JIRA NVGPU-1874
Change-Id: Ida1edae707ddded300f9a629710b53a6606ac0ee
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761338
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Changes:
1. Added a new type: CTRL_PERF_VFE_EQU_OUTPUT_TYPE_THRESHOLD
This parameter was added in VFE table(under index 36) of 4F VBIOS to
convert VFE floating point output into threshold percentage value for
Fmon threshold programming.
Bug 2500899
Change-Id: Ife72e9a7b644c289702b0bcc89a1c9dce9d60386
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011177
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Currently, PMU f/w ucode read is part of ACR prepare ucode blob
which makes PMU to depend on ACR to init PMU f/w version related
ops & to include PMU related members to be part of ACR data struct
to free the allocated space for PMU ucodes.
Moved PMU f/w ucode read to PMU early init function & initializing
version ops once PMU ucode descriptor is available.
JIRA NVGPU-1146
Change-Id: I465814a4d7a997d06a77d8123a00f3423bf3da1e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006339
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Currently clk_arb wq waits only for tasks.
Sometimes this doesnt invoke wq when thread_stop is called.
Add a check for thread_stop when waiting in wq.
Remove atomic_inc when no job is submitted.
Use current_time_ns() instead of ptimer to get time.
Bug 200488054
Change-Id: I770d566dd29371bd189d30dd5e60a6b23a9c98ff
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012244
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-Earlier, with DMEM queue, if command needs in/out payload
then space needs to be allocated in DMEM/FB-surface &
copy payload in allocated space before sending command
by providing payload info in sending command .
-With FBQ, command in/out payload is also part of FB command
queue element & not required to allocate separate space in
DMEM/FB-surface, so added changes to handle FBQ payload request
while sending command & also in response handler to extract
data from out payload.
JIRA NVGPU-1579
Bug 2487534
Change-Id: If3ca724c2776dc57bf6d394edf9bc10eaacd94f9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2004021
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-Added NVGPU_SUPPORT_PMU_RTOS_FBQ feature to enable
FBQ support.
-Add support to read PMU RTOS init message from
FBQ message queue to process init message &
construct FBQ for further communication
with PMU RTOS ucode.
-Added functions to init FB command/message queues
as per init message inputs from PMU RTOS ucode.
JIRA NVGPU-1578
Bug 2487534
Change-Id: Ib6c2b26af3927339bd4fb25396350b3f4d222737
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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In the below scenario
1. nvrm app requests & gets all VF points from nvgpu.
2. nvrm stores all the VF points and starts setting each point.
3. During step 2, VF gets updated in nvgpu due to some events.
4. There is a mismatch b/w points in nvrm and VF table in nvgpu.
5. If nvrm freq is less than nvgpu freq , PMU cant program.
Makesure highest between nvrm and VF table goes to PMU
Bug 200454682
Change-Id: I9c58f129ff1c0dfb3f4759242469b3622fe11bb2
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000238
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