This patch does the following.
1. Remove unused functions from volt_pmu.c.
2. Append public functions with nvgpu.
3. Remove GP106 functions and rename TU104 to generic functions.
4. Rename volt struct from gpu_ops.
5. Remove the unused volt.h header file.
6. Make local functions as static and put in order.
7. Remove unused inclusion on header files.
8. After 4, generic functions can be called directly instead of g->ops.
Jira NVGPU-1956
Change-Id: Icaea0ca817d37cccfc09241baa2f047ec2688169
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076535
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This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.
JIRA NVGPU-1993
Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069688
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Semantics of the engine bootloader bootstrap are to set falcon mailbox0
register to non-zero value and verify that it is cleared to ascertain
successful completion of bootstrap.
Read was done in the engine bl_bootstrap related functions. Hence move
the write as well to those functions.
JIRA NVGPU-1993
Change-Id: I6d04148fbf1d517f0af8b4cfc2ee144d38704647
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034511
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Currenlty struct hs_acr passed to engine falcon bootstrap function
to pass falcon info to the falcon unit to execute the ACR HS bin
using engine falcon, as engine already cached the falcon info as
part its structure so removed struct hs_acr parameter pass.
JIRA NVGPU-2907
Change-Id: I0b647b2763c52e97de0c17cfdd273486138ee404
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069593
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add new power/clock gating functions that can be called by
other units.
New clock_gating functions will reside in cg.c under
common/power_features/cg unit.
New power gating functions will reside in pg.c under
common/power_features/pg unit.
Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable
elpg and also in gr_gk20a_elpg_protected macro to access gr registers.
Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled
and slcg_enabled thread safe.
JIRA NVGPU-2014
Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025493
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MISRA Rule 10.3 prohibits implicit assignment of objects of narrower
size or essential type. This fixes MISRA 10.3 violations in pmu_fw.c
The API set_pmu_cmdline_args_secure_mode() was updated to accept a u8
for the val parameter to avoid unnecessary casts.
The APIs get_perfmon_cmd_init_offsetofvar() and
get_perfmon_cmd_start_offsetofvar() were updated to pass a u32 by
reference to get the offset value so the return value can be used
properly.
JIRA NVGPU-2841
Change-Id: I8ae34531e843022e8bfa9b5c60ad163b0f7fbf5c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027767
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The following changes are made in this patch.
1) nvgpu driver is incorrectly using u32 to store enum values in some
functions. Replaced them with correct type enum nvgpu_fifo_engine
2) change parameter type in nvgpu_engine_get_ids from engine_id[]
to *engine_ids
3) rename some function names to remove redundant characters to make
the name shorter.
4) Removed the initialization of enum nvgpu_fifo_engine in functions
where we assign a value before direct access.
Jira NVGPU-1315
Change-Id: Ic65b40c9cb1e90ad278cb36a00e1c9de51724f27
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2020230
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Added support to disable/skip to load LS PMU based on PMU support flag,
when LS PMU skipped only basic PMU engine ops are needed for HS ACR
to load & execute on PMU engine falcon,
GR LS falcons cold/recovery bootstrap will be taken care by ACR as HS
ACR will be loaded for both case & exits by halting in non-secure mode.
JIRA NVGPU-173
Change-Id: I7288c185a9ca2e18b2689aa8a7e0c27a61dd12f5
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019927
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Currently PMU support enable check is done with multiple
methods which added complexity to know status of PMU
support.
Changed to replace multiple methods with support_pmu
flag to know the PMU support, support_pmu will be updated
at init stage based on platform/chip specific settings
to know the PMU support status.
Cleaned up support_pmu flag check with platform specific
PMU members in multiple places & moved check to
public functions
JIRA NVGPU-173
Change-Id: Ief2c64250d1f78e3b054203be56499e4d1d9b046
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024024
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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As a part of regoranizing clk_arb code, This patch does the folowing
1. Move clk_arb HAL files under common/clk_arb unit.
2. Move clk_arb from common/pmu to common/clk_arb.
3. Append public functions with nvgpu.
4. Make local functions as static.
Jira NVGPU-1966
Change-Id: If45c3dbfc4bbe74fe8d30e33e64894d553f3cda5
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027335
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This patch does the following.
1. Append public functions with nvgpu.
2. Move public functions & structure to include/pmu/clk.
3. Remove inclusion of HW header files in common.
4. Move FREQ_STEP_SIZE_MHZ to clk_prog.h as it is used there.
5. Fix 16.3 and 11.3 Misra Violations.
Jira NVGPU-1965
Change-Id: I268d257d6de9c986e456a666cf6d633fe10fc440
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024992
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This patch does the following.
1. Remove unused functions from pmu_perf.c.
2. Append public functions with nvgpu.
3. Move get_status declaration from vfe_var to include/perf.
4. Rename perf_tu104.c to perf_ps35.c and Makefile changes.
5. Remove the unused perf_tu104.h file.
6. Make local functions as static.
Jira NVGPU-1960
Change-Id: I829d113d994dbfc02a45f29795b5926c58106049
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023886
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The type for the timeout parameter to the NVGPU_COND_WAIT and
NVGPU_COND_WAIT_INTERRUPTIBLE macros was too weak. This updates these
macros to require a u32 for the timeout.
Users of the macros are updated to be compliant as necessary.
This addresses MISRA 10.3 violations for implicit conversions of types
of different size or essential type.
JIRA NVGPU-1008
Change-Id: I12368dfa81b137c35bd056668c1867f03a73b7aa
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017503
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As part of creating zbc as gr subunit, move pmu_save hal function
from zbc to pmu hal.
This hal function is used to pass the information to gpmu
firmware, which should reside as part of pmu.
remove pmu_save hal from zbc.
add save_zbc hal under pmu.
remove unused function gr_gk20a_pmu_save_zbc
JIRA NVGPU-1882
Change-Id: I132dbc7a9ee9755043cd08f288344df447e28af6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018581
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Some of the engine queue related defines are shared by PMU, SEC2 and
queue implementations and currently in gpmuif_cmn.h. Let us add
engine_queue.h header file to club all those defines together.
JIRA NVGPU-1994
Change-Id: I57a889e6d14d954d2660e513994bb87cbb1e5824
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019414
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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engine queue head and tail methods were retrieved from falcon structure.
engine queue initialization can get these methods directly from hal
through params. Also eliminate struct nvgpu_falcon dereference in engine
queue sources to remove inclusion of falcon_priv.h.
JIRA NVGPU-1994
Change-Id: Idbebd5049cfd14eb3fe0e27b2bef8436cc61e101
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016290
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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As we plan to move the queue implementations out of falcon unit let us
rename these as:
1. engine_mem_queue - Generic implementation.
2. engine_dmem_queue - DMEM queue implementation of engine_mem_queue.
3. engine_emem_queue - EMEM queue implementation of engine_mem_queu.
4. engine_fb_queue - FB queue implementation.
JIRA NVGPU-1994
Change-Id: Ic81dcc154b3383d9f75fe57cc01269bda2698b25
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016288
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FB queues handling is different from DMEM/EMEM queues in many aspects.
For e.g. no rewind required, additional queue struct fields, additional
queue operations required only for FB queues, push/pop semantics are
different.
Hence prepare separate structure and APIs for FB queues. PMU will have
to deal with the queue implementation chosen. This patch does the follo-
wing:
1. Update function/structure names to falcon_fb_queue_<op/name>.
2. Export nvgpu_falcon_fb_queue_* structure and functions.
3. Removed rewind function pointer and used direct functions for push,
pop and has_room.
4. PMU wrapper defined to use appropriate queue for empty check -
nvgpu_pmu_queue_is_empty.
5. PMU side updates for handling the work buffer and SEC2 updates for
usage of public queue functions.
JIRA NVGPU-1994
Change-Id: Ia5e40384e6e3f9e81d5dbc3d8138eb091337c086
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016285
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Changes:
1) Separated clk.h which is in /nvgpu/include/pmu
into different units
2) Renamed global functions
Intention: At present /nvgpu/include/pmu/clk.h
consists of structures and functions of different
clock units. It is difficult to work on individual
clk units if this file is not separated into
individual units. All stucts and functions in clk.h
are seperated into different clk units.
Individual private clk units were not touched.
Post this patch, the sebsequent patches would make
changes in the individual clk units.
NVGPU-2707
Change-Id: I7bf9fab38a73bceb451291530a67c70ed343b0cb
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2021704
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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Move ACR code to separate folder under common/acr to
make ACR separate unit. with this, separating ACR blob
construct, bootstrap & ACR chip specific configuration
code to different files.
ACR blob construction code split into two version, as
gm20b & gp10b still uses older ACR interfaces & not yet
moved to Tegra ACR, blob_construct_v0 file can be deleted
once gm20b/gp10b uses Tegra ACR ucode & point to
blob_construct_v1 with simple change.
As ACR ucode can execute on different engine falcon &
should not be dependent on specific engine falcon, used
generic falcon functions/interface to support ACR & doesn't
access any engine h/w registers directly, and files with
chip name has configuration needed for ACR HS ucode & LS
falcons.
JIRA NVGPU-1148
Change-Id: Ieedbe82f3e1a4303f055fbc795d9ce0f1866d259
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017046
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The following changes are done in this patch.
1) gk20a_fifo_get_engine_info() is moved to common/fifo/engine.c
and is renamed to gk20a_fifo_get_active_engine_info() to reflect
accurately the purpose of the function.
2) move the definition of enum fifo_engine to <nvgpu/engines.h> and
add the prefix NVGPU_
3) move the following functions related to engines in fifo_gk20a.c to
common/fifo/engines.c and replace their signature by adding the prefix
nvgpu_engine and removing gk20a_fifo.
gk20a_fifo_get_active_engine_info
gk20a_fifo_engine_enum_from_type
gk20a_fifo_get_engine_ids
gk20a_fifo_is_valid_engine_id
gk20a_fifo_get_gr_engine_id
gk20a_fifo_act_eng_interrupt_mask
gk20a_fifo_engine_interrupt_mask
gk20a_fifo_get_all_ce_engine_reset_mask
Jira NVGPU-1315
Change-Id: I63d9dcd905a0bebcc9a4c65776cf6ec7a0837acf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011298
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Since we plan to separate engine DMEM/EMEM and FB queues into separate
implementations, let's make the engine queue_head and queue_tail APIs
independent of nvgpu_falcon_queue parameter.
JIRA NVGPU-1994
Change-Id: I389cc48d4045d9df8f768166f6a1d7074a69a309
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016283
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Currently clk_arb needs PSTATE to be true for dGPU.
Setting PSTATE only FALSE, causes issue as clk_arb fails.
There is no such dependency of PSTATE on iGPU.
Making it unified with a call to check_clk_arb_support().
This call is implemented based on its dependency in iGPU, dGPU.
check_clk_arb_support returns true if supported, else false.
Jira NVGPU-1948
Change-Id: I108dc12bd6ad8d0e074352080c978b7dda9bee05
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014775
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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