MISRA Advisory Rule 12.3 states that the comma operator should
not be used.
This change fixes several violations of this rule in gr falcon
code.
The remaining violations of this advisory rule will be covered
in a rule-specific deviation record.
JIRA NVGPU-3798
Change-Id: Iea579356ac1da03c6730f738f5316b57e26afa7c
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155616
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Following common and corresponding hal functions are non-safe. They are
either required for intr handling or for debug. Compile them out for
igpu safety release. Moved corresponding HALs to falcon_gk20a.c.
nvgpu_falcon_copy_from_emem
nvgpu_falcon_copy_to_emem
nvgpu_falcon_clear_halt_intr_status
nvgpu_falcon_set_irq
nvgpu_falcon_copy_from_dmem
nvgpu_falcon_copy_from_imem
nvgpu_falcon_print_dmem
nvgpu_falcon_print_imem
nvgpu_falcon_get_ctls
nvgpu_falcon_dump_stats can be used in the safety debug build.
JIRA NVGPU-898
JIRA NVGPU-2214
Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152978
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reduce code complexity of following functions in gr.config unit
gv100_gr_config_init_sm_id_table(complexity : 13)
gr_gv100_scg_estimate_perf(complexity : 23)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create two sub functions from gv100_gr_config_init_sm_id_table function
gr_gv100_scg_estimate_perf_for_all_gpc_tpc(complexity : 5)
gv100_gr_config_set_sminfo(complexity : 3)
and reduce gv100_gr_config_init_sm_id_table complexity to 8
Create four sub functions from
gv100_gr_config_init_sm_id_table function
gr_gv100_find_max_gpc(with complexity : 2)
gr_gv100_remove_logical_tpc(with complexity : 4)
gr_gv100_calc_valid_pes(with complexity : 6)
gr_gv100_scg_calculate_perf(with complexity : 7)
and reduce gr_gv100_scg_estimate_perf complexity to 10
Jira NVGPU-3661
Change-Id: Iaaef1a98f2c6c55cd7b0a1a57d1c74eb09d43869
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156744
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reduce code complexity of following functions in gr.intr unit
gm20b_gr_intr_handle_exceptions(complexity : 13)
tu104_gr_intr_log_mme_exception(complexity : 13)
gv11b_gr_intr_handle_icache_exception(complexity : 17)
gv11b_gr_intr_handle_gpc_gpccs_exception(complexity : 13)
gv11b_gr_intr_handle_l1_tag_exception(complexity : 15)
gv11b_gr_intr_handle_gpc_gpcmmu_exception(complexity : 15)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create following 8 sub functions for handling each exception from
gm20b_gr_intr_handle_exceptions function
gr_gm20b_intr_check_gr_fe_exception(complexity : 2)
gr_gm20b_intr_check_gr_memfmt_exception(complexity : 2)
gr_gm20b_intr_check_gr_pd_exception(complexity : 2)
gr_gm20b_intr_check_gr_scc_exception(complexity : 2)
gr_gm20b_intr_check_gr_ds_exception(complexity : 2)
gr_gm20b_intr_check_gr_ssync_exception(complexity : 4)
gr_gm20b_intr_check_gr_mme_exception(complexity : 3)
gr_gm20b_intr_check_gr_sked_exception(complexity : 2)
and reduce gm20b_gr_intr_handle_exceptions complexity to 3.
Create following 2 sub functions from tu104_gr_intr_log_mme_exception
function
gr_tu104_check_dma_exception(complexity : 6)
gr_tu104_check_ram_access_exception(complexity : 3)
and reduce tu104_gr_intr_log_mme_exception complexity to 6
Create following 2 sub functions for corrected and uncorrected error
reporting from gv11b_gr_intr_handle_icache_exception function
gv11b_gr_intr_report_icache_uncorrected_err(complexity : 5)
gv11b_gr_intr_report_icache_corrected_err(complexity : 5)
and reduce gv11b_gr_intr_handle_icache_exception complexity to 9
Create following 2 sub functions for corrected and uncorrected error
reporting from gv11b_gr_intr_handle_l1_tag_exception function
gv11b_gr_intr_report_l1_tag_uncorrected_err(complexity : 4)
gv11b_gr_intr_report_l1_tag_corrected_err(complexity : 4)
and reduce gv11b_gr_intr_handle_l1_tag_exception complexity to 9
Create following 1 sub function for error reporting from
gv11b_gr_intr_handle_gpc_gpccs_exception function
gv11b_gr_intr_report_gpccs_ecc_err(complexity : 5)
and reduce gv11b_gr_intr_handle_gpc_gpccs_exception complexity to 9
Create following 1 sub function for error reporting from
gv11b_gr_intr_handle_gpc_gpcmmu_exception function
gv11b_gr_intr_report_gpcmmu_ecc_err(complexity : 5)
and reduce gv11b_gr_intr_handle_gpc_gpcmmu_exception complexity to 9
Jira NVGPU-3661
Change-Id: I855b9ba055f3a8578c7b62cd59e249017ec31936
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155852
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Moved debugger/cilp functions from gr ctxsw prog hal files for various
platforms to corresponding fusa files as currently they are enabled in
the safety build. Updated the arch yaml to reflect the non-fusa and
fusa units for gr ctxsw_prog.
JIRA NVGPU-3690
Change-Id: I188d3de223aa65816b5f511b776eb8278e221219
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156877
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.
This change removes five violations of this rule that involve casting
boolean results to unsigned values:
* pass 1/0 (instead of true/false) to nvgpu_atomic operations
* fix skip_mask handling in gm20b_gr_init_pd_skip_table_gpc()
* fix l3_alloc flags check in nvgpu_gmmu_map_locked()
This change also eliminates several MISRA Advisory Rule 4.6 violations.
JIRA NVGPU-3798
Change-Id: I707da8a812bfb32eaeb2200463885c0961b197b3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153070
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.
Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.
Jira NVGPU-3690
Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
used.
Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.
Also, change users of ALIGN to pass unsigned types only.
JIRA NVGPU-3515
Jira NVGPU-3411
Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
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Remove below hals since the corresponding functions are same on all
platforms and they are h/w independent
g->ops.gr.enable_ctxsw()
g->ops.gr.disable_ctxsw()
g->ops.gr.reset()
Call the functions directly at all places
Remove CONFIG_NVGPU_DEBUGGER from places where these functions are
called since they are not debugger dependent
This also helps to disable CONFIG_NVGPU_DEBUGGER and to keep recovery
sequence intact
Jira NVGPU-3506
Change-Id: Id2b208ca23dc4667e78edcd8ad242a8558e0ff64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Fix MISRA 13.2 errors in hal.gr.intr unit.
misra_c_2012_rule_13_2_voilation: In hi32_lo32_to_u64, two function
calls in the arguments for which the order of evaluation is undefined.
Jira NVGPU-3621
Change-Id: I2c0d9a4492068f13edfb6ac6309f8679d1fbcee4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134597
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-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files
JIRA NVGPU-3418
Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr
unit as below
g->ops.gr.intr.set_hww_esr_report_mask()
g->ops.gr.intr.handle_tpc_sm_ecc_exception()
g->ops.gr.intr.get_esr_sm_sel()
g->ops.gr.intr.clear_sm_hww()
g->ops.gr.intr.handle_ssync_hww()
g->ops.gr.intr.log_mme_exception()
g->ops.gr.intr.record_sm_error_state()
g->ops.gr.intr.get_sm_hww_global_esr()
g->ops.gr.intr.get_sm_hww_warp_esr()
g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask()
g->ops.gr.intr.get_sm_hww_warp_esr_pc()
g->ops.gr.intr.tpc_enabled_exceptions()
g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val()
Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to
common.gr.gr unit
All of above functions and hals will be needed in safety build
Jira NVGPU-3506
Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127753
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GPC MMU debug mode should be set if at least one channel
in the TSG has requested it. Add refcounting for MMU debug
mode, to make sure debug mode is disabled only when no
channel in the TSG is using it.
Bug 2515097
Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123017
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This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id
JIRA NVGPU-3516
Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
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This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
the initialization required for errors that can be injected using hw
support, error injection function. Further, it passes the required
information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
nvgpu_report_ecc_err.
Jira NVGPU-3235
Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.
Jira NVGPU-3237
Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.
Jira NVGPU-3248
Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
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