nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc
APIs. So, move the enum into mc.h, and replace the include of unit.h
with mc.h where appropriate. And update the yaml arch.
JIRA NVGPU-4144
Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2216106
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When virtualized, the guest OS has no direct access to
PMU functionality:
- Don't create debugfs entries that rely on PMU access
- Clean up PMU vgpu HAL entries that imply that PMU access
is supported
Bug 200543218
Change-Id: I12730b600802448a240f3de042760041d3ae7d29
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213650
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA rule 17.1 forbids use of stdarg.h features defined for variable
arguments. This patch creates timers.h header for posix and QNX to
change nvgpu_timeout_expired_msg() to macro definition.
Jira NVGPU-4075
Change-Id: I8167f0ff7fdfb74adbbbed9c3021a9df2ad6401b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2200885
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MISRA Rule 17.1 forbids use of stdarg.h features which are defined for
variable arguments.
This patch modifies logging macros to use slogf function for QNX builds.
This avoids use of variable argument functions used for formatting log
message.
Jira NVGPU-4075
Change-Id: I5b6bb1107a7e431afaa960003858193a477b2ee6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2192016
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IRQs were not enabled before nvgpu_finalize_poweron, so debugging early
init issues such as MMU fault, invalid PRIV ring or bus access etc.
triggered during nvgpu power-on was cumbersome. Hence, Enable the
IRQs before nvgpu_finalize_poweron is called.
In HUB (MMU fault) ISR, MMU fault handling is only limited to snapped
in priv reg in case of fault during nvgpu power-on.
In HUB (MMU fault) ISR, access to fault buffers is synchronized as
nvgpu driver reads the fault buffer registers before proceeding
with fault handling. However, additional MMU fault handling
needs to be synchronized with GR/FIFO/quiesce/recovery setup
through nvgpu power-on state.
JIRA NVGPU-1592
Change-Id: I8a5f2fcd79cb7ad8e215359e7a9fad50bfd46d67
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203861
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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IRQs can get triggered during nvgpu power-on due to MMU fault, invalid
PRIV ring or bus access etc. Handlers for those IRQs can't access the
full state related to the IRQ unless nvgpu is fully powered on.
In order to let the IRQ handlers know about the nvgpu power-on state
gk20a.power_on_state variable has to be protected through spinlock
to avoid the deadlock due to usage of earlier power_lock mutex.
Further the IRQs need to be disabled on local CPU while updating the
power state variable hence use spin_lock_irqsave and spin_unlock_-
irqrestore APIs for protecting the access.
JIRA NVGPU-1592
Change-Id: If5d1b5e2617ad90a68faa56ff47f62bb3f0b232b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203860
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As per one of the requirement priority of interrupt threads in
qnx should be changed to 21 with SCHED_RR class. NVGPU driver
is creating threads with FIFO class. This makes delay in scheduling
other interrupt threads.
This is added to change the schduler class to RR.
JIRA NVGPU-4121
Change-Id: Ie0a5f08b95cfab4ffbbd3c0c74a53324c64c202f
Signed-off-by: dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206210
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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Currently after sending change seq RPC, nvgpu waits for a fixed time
of 20ms.
This CL replaces this with pmu_wait_message_cond, which will return
immediately after getting change seq completion event.
Also added debug fs node to get the change seq execution time.
Bug 200545366
Change-Id: Iba283f65d4949858be9cbff88de4d21a8c92ff81
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202423
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golden image size will be set when memory allocated.
See function:
- nvgpu_gr_obj_ctx_init
If golden image size is 0, gr_golden_image should be a NULL
pointer in most cases. So add NULL pointer checking in
tpc_pg_mask_store to avoid NULL pointer exception.
Bug 2403210
Change-Id: I14df5cd94d7a4418c3089c5f84b6eab93c485ba6
Signed-off-by: Sunny Li <sunnyl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161280
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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This patch addresses misra violations due to SDL error reporting
callbacks. In particular, it addresses the following misra violation:
- misra_c_2012_directive_4_7_violation: Calling function
"nvgpu_report_*_err()" which returns error information without testing
the error information.
JIRA NVGPU-4025
Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196895
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ifdef function prototypes with CONFIG_* defines. This fixes MISRA rule
8.6 violations which complain about undefined functions.
Also moved nvgpu_channel_get_from_file prototype to ioctl_channel.h &
nvgpu_probe to driver_common.h as those are linux specific. Define
nvgpu_init_soc_vars in posix/soc.c as it is implemented in QNX.
JIRA NVGPU-3873
Change-Id: I5d2b238e1b5d1318867cd2416ac5f03cc6ab7c6a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196794
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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In some cases, we would get deadlock issue due to there are two locks
acquisition on common clk driver's lock and nvgpu driver's locks. At
the bug, inconsistent lock ordering problem will come with one thread
gets "nvgpu lock -> clk lock" and the other thread gets "clk lock ->
nvgpu lock".
Slove the latter path with one-time initializing clk_parent entry
and use cached data afterward.
Bug 2555115
Change-Id: I31c5c2728f406307e7cfd4e555f4db0c163234d8
Signed-off-by: Jeremy Ho <jeremyh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146727
(cherry picked from commit 42c2bdfb9f)
Reviewed-on: https://git-master.nvidia.com/r/2160290
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Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.
The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.
JIRA NVGPU-3820
Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
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Add posix support for nvgpu_request_firmware and
nvgpu_release_firmware calls.
In x86, needed firmware are copied under userspace/firmware
directory.For jetson, firmware files will be copied under
nvgpu_unit/firmware directory.
Update Makefile.tmk to copy firmware in systemimage under
nvgpu_unit/firmware directory.
Jira NVGPU-3582
Bug 2693908
Change-Id: I5f5e5819dc5501e587bc8afc0a3944c18a8e9bef
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189493
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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This reverts commit 2a7e6a1111c2e52df2eae22fd084f0c955ed0759.
Bug 2693908
Change-Id: Id9ed7a6b18929cf1b319a54aca227c7c36515f26
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189199
Add posix support for nvgpu_request_firmware and
nvgpu_release_firmware calls.
In x86, needed firmware are copied under userspace/firmware
directory. For jetson, firmware files will be copied under
nvgpu_unit/firmware directory.
Update Makefile.tmk to copy firmware under systemimage under
nvgpu_unit/firmware directory
Jira NVGPU-3582
Change-Id: I9ce729af797e59c8d41a1aa4ee964d7d9b8b666e
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2181572
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Replaced ch->mmu_debug_mode_enabled with ch->mmu_debug_mode_refcnt.
If channel is enabled multiple times by userspace, then ref count is
updated accordingly. There is an expectation that enable/disable
calls are balanced for setting channel's mmu debug mode.
When unbinding the channel, decrease refcnt for the channel until it
reaches 0.
Also, removed tsg parameter from nvgpu_tsg_set_mmu_debug_mode as it
can be retrieved from ch.
Bug 2515097
Change-Id: If334e374a55bd14ae219edbfd3b1fce5ff25c226
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2184702
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This patch adds nvgpu API in linux and posix to query vpr resize.
The new API nvgpu_is_vpr_resize_enabled() is used in
nvgpu_submit_channel_gpfifo().
Previously, if non-deterministic channel has timeout disabled and
GPU cannot railgate on some platform, then channel doesn't power ref
count and results in video freeze. To resolve non-determinstic channel
job tracking needs to be enabled if vpr resize is supported or if GPU
can railgate.
Bug 200532122
Change-Id: Icfbff6253762b195b2f5955749343974b1a7a269
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171093
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For safety build, nvgpu driver should enter SW quiesce state
in case an uncorrectable error has occurred. In this state, any
activity on the GPU should be prevented, without powering off the GPU.
Also, a minimal set of operations should be used to enter SW quiesce
state.
Entering SW quiesce state does the following:
- set sw_quiesce_pending: when this flag is set, interrupt
handlers exit after masking interrupts. This should help mitigate
an interrupt storm.
- wake up thread to complete quiescing.
The thread performs the following:
- set NVGPU_DRIVER_IS_DYING to prevent allocation of new resources
- disable interrupts
- disable fifo scheduling
- preempt all runlists
- set error notifier for all active channels
Note: for channels with usermode submit enabled, userspace can
still ring doorbell, but this will not trigger any work on
engines since fifo scheduling is disabled.
Jira NVGPU-3493
Change-Id: I639a32da754d8833f54dcec1fa23135721d8d89a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2172391
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- Add doxygen documentation.
- Remove unused fields of nvgpu_tsg struct:
-- timeslice_timeout
-- timeslice_scale
- Remove unused functions:
-- nvgpu_tsg_set_runlist_interleave
- nvgpu_tsg_post_event_id is not supported in safety build.
This function is moved under CONFIG_NVGPU_CHANNEL_TSG_CONTROL
compiler flag.
- Below functions are moved under CONFIG_NVGPU_KERNEL_MODE_SUBMIT
nvgpu_tsg_ctxsw_timeout_debug_dump_state
nvgpu_tsg_set_ctxsw_timeout_accumulated_ms
- Rename
gk20a_is_channel_active -> nvgpu_tsg_is_channel_active
release_used_tsg -> nvgpu_tsg_release_used_tsg
- nvgpu_tsg_unbind_channel_common declared static
- Fix build issue when CONFIG_NVGPU_CHANNEL_TSG_CONTROL is disabled
Remove CONFIG_NVGPU_CHANNEL_TSG_CONTROL for
nvgpu_gr_setup_set_preemption_mode as it is needed in safety build.
By default compute preemption mode will be set to WFI. CUDA will
change it to CTA during context init time.
JIRA NVGPU-3595
Change-Id: I8ff6cabc8b892c691d951c37cdc0721e820a0297
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151489
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test_falcon_halt failed as nvgpu_timeout_expired returned -ETIMEDOUT when
time equal to timeout is reached and nvgpu_timeout_peek_expired returns
false when time is equal or less and true when time is greater than
timeout, leading to inconsistent return value.
Update nvgpu_timeout_expired_msg_cpu logic that is used by former.
JIRA NVGPU-3946
Change-Id: I365063cc12a584833c08ca710bb795c0e9d814cd
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180233
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Changes added to support "rmmod nvgpu" in dgpu simulation after gpu
poweron.
nvgpu_engine-wait_for_idle got stuck in busy mode for nvdec and nvec
engines in simulation as simulation doesnt support timeout.
These engines are not valid engines in nvgpu engine list.
Add nvgpu_engine_check_valid_id before checking engine status.
Simulation crash on accessing 0xb81604 top interrupt register.
Add func_priv_cpu_intr_top__size_1_v() function to get the supported
size than using default MAX_INTR_TOP_REGS.
nvlink is not supprted in dgpu simulation. Avoid warning for
-ENODEV return.
Avoid register read following gpu power off completion.
Bug 2498574
Change-Id: I9f9f1cf1ac4620242bda1d2cc0f29f51f81a6711
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2179930
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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CE app functionality from nvgpu is non-safe for igpu. CE engines init
/reset/cg related functionality is required in safety. Hence move the
CE app logic under CONFIG_NVGPU_DGPU flag and update the sources
accordingly.
JIRA NVGPU-3814
Change-Id: I37aa00b1184baccd5fe569ec315be60ac42dac9b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168956
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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For dGPU with PCIE interface do not have a thermal alert pin.
Only platforms where dGPU is used with SXM interface have the
thermal alert pin.
This change makes sure that if nvgpu-therm-gpio DT entry is
is missing we don't fail probe but continue with GPU
initialization without enabling thermal alert feature.
Bug 200542024
Change-Id: Iaf3aec9b66695a45daf86ecfdeec398b66f96bfd
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2173495
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