This patch moves MM HALs that are guaranteed to be functionaly safe
into _fusa.c files. HALs that are not part of FUSA are not compiled
anymore when the safety profile is enabled.
Given a HAL source file:
- it may contain only FUSA code, in that case the source file is
simply renamed with the _fusa postfix.
- it may contain only non-FUSA code, in that case the file is left
as-is
- it may contain a mix, in that case the original file will now only
contain non-FUSA code, and all FUSA code will be moved into a new
source file with the _fusa postfix.
JIRA NVGPU-3690
Change-Id: I44c604aef2d72252abb7da1c0ef1210d71a0efa7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140895
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Fix MISRA C-2012 Rule 10.3 error in common.gr unit
misra_c_2012_rule_10_3_violation: Implicit conversion of
"!!(gr->ctxsw_disable_count < 0)" from essential type "boolean" to
different or narrower essential type "signed 32-bit int".
Jira NVGPU-3622
Change-Id: I27fb1aa64906242230678dff345307eb0a2d7bdc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140940
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Fix MISRA C-2012 Rule 10.8 error in common.gr unit
misra_c_2012_rule_10_8_violation: Cast from 16 bit width expression
to a wider 64 bit type.
Jira NVGPU-3622
Change-Id: Ie3edbb338c0914f37d0b249845ea014c0ba964d2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140939
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This patch fixes violations for below listed rules in
nvgpu/common/mm/as.c.
MISRA Rule 10.3 forbids implicit conversion of an essential type to
different or narrower essential type.
MISRA rule 10.4 requires essential type of left hand operand to be same
as right hand operand.
MISRA Rule 21.8 requires the size_t argument of strncpy() to be less
than length of the source string.
Change-Id: I4ff1e4dbbd602baf906af8230c6902249e0223e8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2142566
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Safety build does not support vidmem. This patch compiles out vidmem
related changes - vidmem, dma alloc, cbc/acr/pmu alloc based on
vidmem and corresponding tests like pramin, page allocator &
gmmu_map_unmap_vidmem..
As vidmem is applicable only in case of DGPUs the code is compiled
out using CONFIG_NVGPU_DGPU.
JIRA NVGPU-3524
Change-Id: Ic623801112484ffc071195e828ab9f290f945d4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132773
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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File vgpu_fifo_gv11b.c contained syncpoint related implementation
specific to gv11b. Move the implementations to a new file in
hal directory for vgpu hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.c.
Also move function vgpu_gv11b_init_fifo_setup_hw() to a new
file in hal directory for vgpu hal/vgpu/fifo/fifo_gv11b_vgpu.c.
Add a new yaml file nvgpu-hal-vgpu.yaml that contains vgpu
specific hal files. Update arch yaml to reflect the above changes.
Jira GVSCI-994
Change-Id: Ie33614473d5fd3fcd624c70709b109c4e45725ef
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2138390
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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vgpu_gv11b_tsg_bind_channel() was specific to gv11b. Modify
function vgpu_tsg_bind_channel() to handle gv11b specific
case by checking if subctx is supported.
Delete gv11b specific file common/vgpu/gv11b/vgpu_tsg_gv11b.c
and update arch yaml file accordingly.
Jira GVSCI-994
Change-Id: I36c1f7392087573afa06cd3652a145aa92055f1c
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2138389
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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Add a doxygen build to nvgpu. Use the following command from the
drivers/gpu/nvgpu directory:
$ make -f Makefile.doxygen
This will autogenerate a list of files from the safety profile
architecture and then generate doxygen documentation from said
list of files.
Also add a .gitignore entry for the sources file that gets
generated during the build.
JIRA NVGPU-3544
Change-Id: I2415de631efcc8447c81ace1700ebac8b69a89df
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131051
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
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- This patch replaces "nvgpu_current_time_ms" with "nvgpu_hr_timestamp_us".
- "nvgpu_hr_timestamp_us" gives timestamp in microseconds and has better
accuracy than "nvgpu_current_time_ms" (which gives timestamp in millisecond)
Bug 200503143
Change-Id: I6a10e8e1b3e8ff842aa23f58bf2ba9344af232a6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125959
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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INT30-C Requires that unsigned integer operations do not wrap.
INT31-C Requires that integer conversions do not result in lost or
misinterpreted data.
ERR33-C Requires to detect and handle standard library errors.
Fix the above CERT C violations in kmem unit.
Jira NVGPU-3603
Change-Id: I104551406e3cf6d2da22c5b6c6edc6694992ce62
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139529
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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Modify nvgpu_gr_checksum_u32 code from
(u32)(((u64)a + (u64)b) % (U32_MAX))
to nvgpu_safe_cast_u64_to_u32(((u64)a + (u64)b) & (U32_MAX)).
This function returns the last 32bits.
Jira NVGPU-3622
Change-Id: I8d348a624a5930b7ba813b0a74af270b49b03844
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140254
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Right now in PMU we have disabled usage of VFE cached
values as we have seen failures in 5.1.3.0 release.
This patch will send vfe_equ dependent masks to PMU which
will be used for initial invalidation of dependent VFE_EQU
cached values. As a result PMU will compute the dependent
EQUs and cache them.
NVGPU-3645
Change-Id: If99960481317a09df9499265650162245f404555
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137867
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Right now in PMU we have disabled usage of VFE cached values
as we have seen failures in 5.1.3.0 release. This patch
will send vfe_var dependent masks to PMU which will be
used for initial invalidation of dependent VFE_VAR cached
values. As a result PMU will compute the dependent VARs and
cache them.
NVGPU-3645
Change-Id: I814ae819d77270ac45b97cf2a32726992e6f4af3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137423
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Remove below hals since the corresponding functions are same on all
platforms and they are h/w independent
g->ops.gr.enable_ctxsw()
g->ops.gr.disable_ctxsw()
g->ops.gr.reset()
Call the functions directly at all places
Remove CONFIG_NVGPU_DEBUGGER from places where these functions are
called since they are not debugger dependent
This also helps to disable CONFIG_NVGPU_DEBUGGER and to keep recovery
sequence intact
Jira NVGPU-3506
Change-Id: Id2b208ca23dc4667e78edcd8ad242a8558e0ff64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
