-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files
JIRA NVGPU-3418
Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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Add an assert check to ilog2() before subtracting to avoid CERT-C INT30
violation. Rule INT30 requires checking for overflow of signed values.
JIRA NVGPU-3563
Change-Id: Ieff968e6245e61150396746d78d69558f22338af
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128587
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Initially, EXPECT_BUG was implemented with a if (!setjmp) which was
semantically incorrect for the setjmp construct and caused a MISRA
violation. Upon fixing the MISRA violation, it was changed to
if (setjmp != 0) which fixed the MISRA violation but made the test
code to never actually run because setjmp will first return 0 during
the init of the jump point. This caused EXPECT_BUG to always return
true as if a BUG() occurred.
In addition, setjmp is relying internally on CPU registers. As a
result, local variables may get clobbered. This mainly happens when
compiler optimizations are enabled (release builds) and the compiler
relies more on registers to hold local variables. In the case of the
EXPECT_BUG statement expression, the variable holding the return value
was incorrectly getting clobbered in some corner cases leading to
false negatives. The easy workaround for this is to declare it as
volatile, which prevents the compiler from only relying on registers
for this variable.
JIRA NVGPU-3562
Change-Id: Ie5e262d630bdd38b22449347a396d4c2cdd3bbe2
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126872
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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A separate bug caused EXPECT_BUG to always return true without actually
calling the corresponding test code. This hid some issues in the buddy
allocator unit where the fini() operation was called several times while
expecting it to call BUG(). Doing so caused the mutex unlock operation to
not be called, which caused a deadlock for all subsequent calls. The fix
is to explicitly release the mutex after each call to fini() that expects
a BUG().
JIRA NVGPU-3562
Change-Id: Ic26058a272c616d2a6052d319f38a4d4dc33ef1c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126874
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Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.
This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.
Jira NVGPU-3476
Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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Unit tests in page_table were initializing the VM with a kernel_reserved
section that was slightly smaller than expected. Then, when the fixed
alloc to support semaphores was done, the fixed address used was actually
below the start of the kernel address space. As a result this caused an
overflow in the base shift in the buddy allocator responsible for
managing the fixed alloc.
Change-Id: I4e688d418262ac8d9d4b66b46bd32ca5456d95e8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130433
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Tested-by: Philip Elcan <pelcan@nvidia.com>
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The patch adds missing parentheses for macros used in SDL. It is required to
address the following misra violation: MISRA C-2012 Rule 20.7 - Macro parameter
expands into an expression without being wrapped by parentheses.
JIRA NVGPU-3180
Change-Id: I70d5359652c6e29814fe17e356dcd5553b498b34
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130260
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Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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The vm object num_user_mapped_buffers was declared as an int. However,
it is an unsigned value. Being a signed value required a cast to
unsigned when calling nvgpu_big_zalloc() which causes a CERT-C INT31
violation. So, avoid the cast and use an unsigned type. And fix related
INT30 violations related to num_user_mapped_buffers as well.
To avoid introducing new MISRA/CERT-C violations, update the upstream
user of these changes, fifo/channel.c and make the equivalent uses of
this value, num_mapped_buffers a u32 as well.
JIRA NVGPU-3517
Change-Id: I6f6d9dfe4a0ee16789b8cd17b908a3f3f9c4a40c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127427
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Rule INT31 requires integer conversions do not result in losing or
misinterpreting data. For most cases, use the safe cast operations.
For one case, the conditional operator was being used for s16 values
which were being promoted to ints. So, replace the conditional operator
with an if statement.
JIRA NVGPU-3517
Change-Id: Iac466911b0dd3893e7e7a188e372272b14591b60
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127425
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- Fix Rule 16.1 and 16.6 violations:
Every switch statement shall have at least two
switch-clauses
- Fix Rule 15.6 violations:
The body of an iteration statement shall be a
compound statement.
- Fix Rule 17.7 violations:
The return value of a non-void function shall
be used.
JIRA NVGPU-3546
Change-Id: I475d185945f0998d4d359f4b9ded6e983474f01f
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127923
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Function for copying to/form IMEM/DMEM cast pointer to char to
pointer to u32 since falcon data registers are read/written in
4-bytes. Firmware data is generally byte stream and hence we
won't be able to deal in pointer to u32. Hence we need deviate
from misra rule 11.3.
Firmware data is also not aligned at word boundary sometimes
hence we need to copy it byte by byte to conform to the dev-
iation recommendation.
Error: MISRA C-2012 Rule 11.3: ./hal/falcon/falcon_gk20a.c:296:
misra_violation: The object pointer expression "src" of type
"u8 *" is cast to type "u32 *".
JIRA NVGPU-3271
Change-Id: Ic081f97226dbbcf08402970829624933402066eb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108547
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Move all unit test specific code in bug unit under the define
__NVGPU_UNIT_TEST__. With this change the following MISRA violations
in bug unit will be only for UT specific code,
MISRA rule 11.3
MISRA rule 21.4
MISRA rule 21.5
Jira NVGPU-3294
Change-Id: I54d3fc2bb6f1f8bc319443c522cb7036d37368e6
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129285
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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Fix CERT INT30-c issue in gr falcon driver replacing
u32 arithmetic operation with nvgpu_safe_add_u32.
Also replaced SZ_256 with 256U to avoid mixed math calculation
with u32 and UL.
JIRA NVGPU-3413
Change-Id: If4f52845a78b7dc0c7936040d759471ba2e5ffc1
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126840
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Hal API g->ops.gr.halt_pipe() is defined in unsafe unit hal.gr.gr
It is called from safe unit, and it calls into API
g->ops.gr.falcon.ctrl_ctxsw() which is also safe
Hence get rid of unsafe API g->ops.gr.halt_pipe().
Caller now directly calls hal.gr.falcon API to halt pipe
Jira NVGPU-3506
Change-Id: I5439cb79431795fc7c22384832cf632d6db03316
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127755
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Trap handling and SM preprocessing is not needed in safety build i.e.
when NVGPU_DEBUGGER is false
Add NVGPU_DEBUGGER flag for all unsafe processing.
In safety build we only report the SM exceptions and return error
so that recovery is triggered
Also add flag for gr_intr_post_bpt_events() since event handling
is not needed in safety build
Jira NVGPU-3506
Change-Id: I660930fdb185b82c0adb612decbfd3d014ce2524
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127754
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Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr
unit as below
g->ops.gr.intr.set_hww_esr_report_mask()
g->ops.gr.intr.handle_tpc_sm_ecc_exception()
g->ops.gr.intr.get_esr_sm_sel()
g->ops.gr.intr.clear_sm_hww()
g->ops.gr.intr.handle_ssync_hww()
g->ops.gr.intr.log_mme_exception()
g->ops.gr.intr.record_sm_error_state()
g->ops.gr.intr.get_sm_hww_global_esr()
g->ops.gr.intr.get_sm_hww_warp_esr()
g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask()
g->ops.gr.intr.get_sm_hww_warp_esr_pc()
g->ops.gr.intr.tpc_enabled_exceptions()
g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val()
Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to
common.gr.gr unit
All of above functions and hals will be needed in safety build
Jira NVGPU-3506
Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127753
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Compile out engine-queue code used for command/message
communication between NVGPU-PMU/SEC2 RTOS which are
non-safe for safety build, compiled out unit by setting
NVGPU_FEATURE_ENGINE_QUEUE build flag to 0.
JIRA NVGPU-3568
Change-Id: I9553b11804b70ec9d109ceecc4b5288cf6b48816
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128485
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GPC MMU debug mode should be set if at least one channel
in the TSG has requested it. Add refcounting for MMU debug
mode, to make sure debug mode is disabled only when no
channel in the TSG is using it.
Bug 2515097
Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123017
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This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id
JIRA NVGPU-3516
Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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The utils unit contains utilities that are useful to everyone. Things
like rbtree, enabled, string, etc go here. This helps prevent clutter
in the top level common directory. Also by organizing source code into
these top level units we reduce our SWUD burden: all utility code may
be described by one SWUD instead of many tiny SWUDs.
JIRA NVGPU-3544
Change-Id: Idc6169f375ba87b8a5d325712bf09aee8f27fb96
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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While preparing the userspace builds for safety, one flag for
fault injection went missing from the host userspace build. This
patch adds it back so that the compile flags for host are the same
as the ones defined in NV_COMPONENT_CFLAGS for target.
JIRA NVGPU-1246
Change-Id: Ia448622f7000ebd46b3b8a17520e30a4f6ccfed9
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128481
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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